The Systolic Array Implementation of Discrete Fourier Transform

江波; 钱惠生

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The Systolic Array Implementation of Discrete Fourier Transform

更新时间：2025-12-08

- The Systolic Array Implementation of Discrete Fourier Transform
- Acta Electronica Sinica Issue 4, (1995)
- 作者机构：
  
  杭州电子工业学院
- 作者简介：
- 基金信息：
- DOI：
  CLC： TN911.1
- Published：1995
- 稿件说明：
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[1]江波,钱惠生.离散傅里叶变换的脉动阵列实现[J].电子学报,1995(04):53-56.

江波, 钱惠生. The Systolic Array Implementation of Discrete Fourier Transform[J]. Acta Electronica Sinica, 1995, (4).
[1]江波,钱惠生.离散傅里叶变换的脉动阵列实现[J].电子学报,1995(04):53-56. DOI：

江波, 钱惠生. The Systolic Array Implementation of Discrete Fourier Transform[J]. Acta Electronica Sinica, 1995, (4). DOI：

摘要

本文提出了离散傅里叶变换（也可以是离散哈特莱变换）的ＶＬＳＩ结构实现方法─脉动（Ｓｙｓｔｏｌｉｃ）阵列实现方法。在实数域内基于并行戈泽尔算法及三角函数递推公式提出了四种处理单元，由此得到了四种脉动阵列结构，其中三个阵列结构是一维的，一个阵列结构是二维变换的，并用传算器（Ｔｒａｎｓｐｕｔｅｒ）作为这些阵列结构的模拟性能验证。这些阵列结构具有高度的并行性，而且阵列结构十分简单，且有模块化和规则化，能够支持高速计算流，因此这些结构便于ＶＬＳＩ结构实现。

Abstract

we put forward the implementation with VLSI structure systolic array.we present four kinds of procesing cells based on paralleled algorithm and recurrence formula of triangle.So we inferenced four kinds of systolic array.One is two-dimensional

the others are one-dimensional.And WE also test and verify the function of the arrays on Transputer.These arrays are greatly parralleled and very simple

regular and modular.So these structures are simple with VLSI structur impementation.

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