Parallel Layout Parameter Extraction on Transputer Parallel Accelerator

吴启明; 党慧; 王泽毅

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Parallel Layout Parameter Extraction on Transputer Parallel Accelerator

更新时间：2025-12-08

- Parallel Layout Parameter Extraction on Transputer Parallel Accelerator
- Acta Electronica Sinica Issue 8, (1995)
- 作者机构：
  
  清华大学计算机科学与技术系
- 作者简介：
- 基金信息：
- DOI：
  CLC： TP391.41
- Published：1995
- 稿件说明：
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[1]吴启明,党慧,王泽毅.在Transputer并行加速器上实现并行的版图参数提取[J].电子学报,1995(08):1-5.

吴启明, 党慧, 王泽毅. Parallel Layout Parameter Extraction on Transputer Parallel Accelerator[J]. Acta Electronica Sinica, 1995, (8).
[1]吴启明,党慧,王泽毅.在Transputer并行加速器上实现并行的版图参数提取[J].电子学报,1995(08):1-5. DOI：

吴启明, 党慧, 王泽毅. Parallel Layout Parameter Extraction on Transputer Parallel Accelerator[J]. Acta Electronica Sinica, 1995, (8). DOI：

摘要

本文叙述ＶＬＳＩＣＡＤ中版图参数提取并行算法在Ｔｒａｎｓｐｕｔｅｒ并行加速器上的实现。参数提取的并行算法是利用图形运算的区域并行性将版图划分为与处理器数目相等的若干区域，然后并行地在各处理器中完成对应区域的版图参数提取，用保持划分区域内图形向量数相等的方法，使各处理器负载均衡，经计算证实，各处理器负载均衡性较好，大大提高了运行速度，Ｔｒａｎｓｐｕｔｅｒ并行加速器具有优良的性能价格比，在其上实现并行的版图参数提取有极大的实用价值。

Abstract

The parallel algorithms of layout parameter extraction on Transputer parallel accelerator in VLSI CAD are described.In the algorithms the region parallelism of graphic operation is utilized.The layout is partitioned into a number of slices and each slice is sent to a processor.The parameter extraction is parallelly implemented on all silces.In order to keep load balance between processors

every partitioned slice contains the same number of graph vectors.The computional results indicate that the load balance between processors is quite satisfactory and the execution time is remarkably reduced.Since the Transputer parallel accelerator possesses excellent ratio of performance to cost

the realization of parallel parameter extraction is of significant value.

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