The Analysis and Design of the Multi-Valued CMOS Current Multiplier

杨洪利; 靳东明; 李志坚

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The Analysis and Design of the Multi-Valued CMOS Current Multiplier

更新时间：2025-12-08

- The Analysis and Design of the Multi-Valued CMOS Current Multiplier
- Acta Electronica Sinica Issue 2, (1995)
- 作者机构：
  
  清华大学微电子所
- 作者简介：
- 基金信息：
- DOI：
  CLC： TP332.22
- Published：1995
- 稿件说明：
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[1]杨洪利,靳东明,李志坚.电流型CMOS多值乘法器分析与芯片的设计[J].电子学报,1995(02):78-81.

杨洪利, 靳东明, 李志坚. The Analysis and Design of the Multi-Valued CMOS Current Multiplier[J]. Acta Electronica Sinica, 1995, (2).
[1]杨洪利,靳东明,李志坚.电流型CMOS多值乘法器分析与芯片的设计[J].电子学报,1995(02):78-81. DOI：

杨洪利, 靳东明, 李志坚. The Analysis and Design of the Multi-Valued CMOS Current Multiplier[J]. Acta Electronica Sinica, 1995, (2). DOI：

摘要

本文以电流型ＣＭＯＳ电路为基础，提出了种一高速、高集成度的多值乘法器设计方案，讨论了多值乘法器与集成度、速度和精度的关系，同时用改进ＣＭＯＳ工艺实现了３×３位８值乘法器的设计，得到了较理想的结果。

Abstract

By using the current-mode CMOS circuit

the multi-valued multiplier of high speed and high density is proposed.A 3×3 bit 8-valued multiplier is designed and the ideal regult is obtained.

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