CMOS Low Noise Amplifier Design

李联; 姜黎

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CMOS Low Noise Amplifier Design

更新时间：2025-12-08

- CMOS Low Noise Amplifier Design
- Acta Electronica Sinica Issue 11, (1994)
- 作者机构：
  
  复旦大学国家专用集成电路和系统重点实验室
- 作者简介：
- 基金信息：
- DOI：
  CLC： TN722.71
- Published：1994
- 稿件说明：
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[1]李联,姜黎.心电图机专用IC－CMOS低噪声前置放大器的设计[J].电子学报,1994(11):87-89.

李联, 姜黎. CMOS Low Noise Amplifier Design[J]. Acta Electronica Sinica, 1994, (11).
[1]李联,姜黎.心电图机专用IC－CMOS低噪声前置放大器的设计[J].电子学报,1994(11):87-89. DOI：

李联, 姜黎. CMOS Low Noise Amplifier Design[J]. Acta Electronica Sinica, 1994, (11). DOI：

摘要

ＣＭＯＳ低噪声、低漂移、低失调运放是为＂心电图机专用集成电路＂而设计的，要求具有高输入阻抗、高ＣＭＲＲ、低漂移、低失调、尤其是低的１／ｆ噪声。ＣＭＯＳ器件与双极型器件和ＪＦＥＴ器件相比，通常有较大的１／ｆ噪声电压。由于采用特殊的设计技术，使我们研制的ＣＭＯＳ运放具有较低的１／ｆ噪声，且功耗较低。经研制及投片，实例得０．０５Ｈｚ～２５０Ｈｚ等效输入噪声电压峰峰值小于２．５μＶ，±２．５Ｖ到±１０Ｖ电源电压下输入失调小于１ｍＶ，共模抑制比１１０ｄＢ以上，完全达到设计指标。该运放可广泛用于生物医学电子学及其他需要低噪声运放的场合，在±２．５Ｖ工作时亦可作为微功耗运放使用。

Abstract

A low noise

low offset voltage

high CMRR and PSRR CMOS operatiorial amplifier is presented.The tested input noise voltage is less then 2.5μV peak to peak..The input offset is less than lmV for supply voltage from±2.5V￣±10V experimental and expected results are in good agreement.

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