Deep Level Studies of Interfacial Traps of P-lnP Metal-Insulator-Semiconductor Structure

Lu Liwu; Zhou Jie

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Deep Level Studies of Interfacial Traps of P-lnP Metal-Insulator-Semiconductor Structure

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- Deep Level Studies of Interfacial Traps of P-lnP Metal-Insulator-Semiconductor Structure
- Acta Electronica Sinica Issue 11, Pages: 72-75(1993)
- 作者机构：
  
  1. 半导体超晶格国家重点实验室中国科学院半导体研究所
  2. 中国科学院半导体研究所北京 100083
- 作者简介：
- 基金信息：
- DOI：
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- Published：1993
- 稿件说明：
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[1]卢励吾,周洁,瞿伟,张盛廉.P-InP MIS结构界面陷阱的深能级研究[J].电子学报,1993(11):72-75.

Lu Liwu, Zhou Jie. Deep Level Studies of Interfacial Traps of P-lnP Metal-Insulator-Semiconductor Structure[J]. Acta Electronica Sinica, 1993, (11): 72-75.
[1]卢励吾,周洁,瞿伟,张盛廉.P-InP MIS结构界面陷阱的深能级研究[J].电子学报,1993(11):72-75. DOI：

Lu Liwu, Zhou Jie. Deep Level Studies of Interfacial Traps of P-lnP Metal-Insulator-Semiconductor Structure[J]. Acta Electronica Sinica, 1993, (11): 72-75. DOI：

摘要

对经PECVD（Plasma Enhanced Chemical Vapor Deposition）生长的P-InP MIS结构的界面陷阱进行了研究。样品介质膜生长是在特定条件下进行的。分别利用C-V和DLTS（Deep Level Tran sient Spectroscopy）技术进行研究。结果表明

在介质膜和InP之间的InP一侧有界面陷阱存在

并获得了与之有关的深能级参数。这些陷阱可能是在不同生长条件的介质膜淀积过程中等离子体引进的有关辐照损伤。

Abstract

The interfacial traps of P-InP MIS structure samples grown by PECVD have been studied using C-V and DLTS techniques.The insulating layers were grown under special conditions.Experimental results show that the interfacial traps are located in the interface between the insulator and InP

and near the interface in the InP.We obtain the deep level parameters associated with the interfacial traps.The origin of these traps might be due to irradiation damage induced by plasma during insulating layer growth process.

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