High Level Array Processors Synthesis of Digital Signal Processing

Xu Chao; Zhang Zengyan; Zhao Wenqing; Tang Pushan

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High Level Array Processors Synthesis of Digital Signal Processing

更新时间：2025-12-08

- High Level Array Processors Synthesis of Digital Signal Processing
- Acta Electronica Sinica Issue 5, Pages: 1-9(1993)
- 作者机构：
  
  1. 复旦大学电子工程系
  2. 复旦大学电子工程系上海 200433
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：1993
- 稿件说明：
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[1]许超,张增雁,赵文庆,唐璞山.行为级DSP算法描述的阵列处理器综合方法研究[J].电子学报,1993(05):1-9.

Xu Chao, Zhang Zengyan, Zhao Wenqing, et al. High Level Array Processors Synthesis of Digital Signal Processing[J]. Acta Electronica Sinica, 1993, (5): 1-9.
[1]许超,张增雁,赵文庆,唐璞山.行为级DSP算法描述的阵列处理器综合方法研究[J].电子学报,1993(05):1-9. DOI：

Xu Chao, Zhang Zengyan, Zhao Wenqing, et al. High Level Array Processors Synthesis of Digital Signal Processing[J]. Acta Electronica Sinica, 1993, (5): 1-9. DOI：

摘要

本文提出了针对递归DSP算法的高层次系统综合流程

并以脉动（systolic）式处理器阵列结构实现.从DSP算法的FDDL行为级描述开始

经由编译及划分

产生数据相关流图（Data Dependency Graph）

然后实现对算法流图的空间映射及时域规划

得到算法的信号流图（Signal Flow Graph）

经时序重构

生成脉动阵列

最后实现对处理器单元的数据路径综合及控制器综合

并对处理器单元定位

本文同时提出了各设计阶段的算法策略及优化策略

并给出综合结果。

Abstract

A high level architectural synthesis procedure on DSP is given in the paper. An architecture of Systolic Array Processors is implemented in the DSP synthesis system. Starting from FDDL（1） behavorial description of DSP algorithms

a list of procedures as parsing

partitioning

DDG （Data Dependency Graph） generation

space projection & scheduling

retiming

data-path allocation are needed to generate the systolic processors array of an application-specific DSP algorithm. The synthesis algorithms and optimization strategies in each design stage are also studied

and some results are illustrated.

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