A global wiring refinement method based on mixed graph model is presented in this paper. The mixed graph model is the consequence of a series of precise vertex decomposition applied to the digraph representation of a floorplan. The graph model is utilized for new expression of global wiring information. Effects of global wiring on chip area can then be estimated and optimized in the layout refinement stage. Global wiring is automatically revised

so placement is affected and improved by wiring and block arrangement. Satisfactory results were obtained by several runs on practical chips.