Wang Yang. Design and Applications of programmable Neural Network Chip with Floating Gate NMOS Transistors[J]. Acta Electronica Sinica, 1992, (10): 50-55.DOI:
Design and Applications of programmable Neural Network Chip with Floating Gate NMOS Transistors
摘要
本文设计了一种浮栅NMOS晶体管神经网络
其结构简单、占用芯片面积小、连接强度可连续调整
同时
还具有分布神经元结构特点
可级联成大网络.用3μm浮栅NMOS工艺制造出的8×8全互连神经网络芯片
它有128个可编程浮栅NMOS晶体管
相当于8个神经元构成的全互连网络.以阿拉伯数字识别和二值图象处理为例
研究结果表明
该网络具有实用前景
且有很大灵活性
同时由于结构简单和适合集成电路工艺特点而便于制造。
Abstract
A neural network with floating gate transistors has been designed. It has the features of continuously changed weights
simple structure
small size units
etc. These chips can be cascaded to form a large network due to characteristics of distributed neuron structure. Therefore
this network is feasible for various applications. 8×8 full interconnected neural network chip has been fabricated in 3μm floating gate NMOS process. It is composed of 128 programmable floatimg gate NMOS transistors
which corresponds to full interconnected network with 8 neurons. The specific applications for the chip has been studied as digit recognition and binary image processing. The results demonstrate that it has prospects of actual applications and large flexibility. In addition
it is easy to be fabricated since the structure is simple and suitable for IC process.