Channel Routing Algorithm by Free Layer Assignment

Qin Donglei

您当前的位置：

首页 >

文章列表页 >

Channel Routing Algorithm by Free Layer Assignment

更新时间：2025-12-08

- Channel Routing Algorithm by Free Layer Assignment
- Acta Electronica Sinica Issue 8, Pages: 14-22(1992)
- 作者机构：
  
  1.   江南大学电子工程系
  2.   中科院北京软件实验室IC-CAD部无锡 214063
  3.   北京 100083
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：1992
- 稿件说明：
移动端阅览
[1]秦冬雷,庄文君.基于自由分层的通道区布线算法[J].电子学报,1992(08):14-22.

Qin Donglei. Channel Routing Algorithm by Free Layer Assignment[J]. Acta Electronica Sinica, 1992, (8): 14-22.
[1]秦冬雷,庄文君.基于自由分层的通道区布线算法[J].电子学报,1992(08):14-22. DOI：

Qin Donglei. Channel Routing Algorithm by Free Layer Assignment[J]. Acta Electronica Sinica, 1992, (8): 14-22. DOI：

摘要

本文在分析线网之间关系的基础上提出了自由分层条件下的通道区布线模型:同层限制图Gs

相交图Gi

基于这一模型

分析了二层布线条件下对线网分层和布线序的基本限制

导出了分层的基本原则

在此基础上

分析了线网可Overlap的性质和条件

从总体分析的思想出发

提出了直接以完成布线通道区所需面积最小化为目标的分层布线算法

实验结果表明

通道区布线面积和通孔的致目比基于横竖分层的布线算法有较大减少

对于Deutsch′s diffjcult example

该算法获得18个track解。

Abstract

A new channel routing model

while allows horizontal and vertical wire seg-ments to be placed on both layers

and two wires on different layer can be overlapped

is pre-sented. Based on this model

the constraints as well as the rules to layer assignment and routing order of nets in the two-layer channel routing are obtained. Then the property of opti-mal overlapping in a zone is analysed. By means of this property

the algorithm determines layer assignment and routing order of nets acoording to global optimat analysis. The routing area and number of vias are reduced much more than the router based on traditional Gv

Gh graph model. Preliminary experimental results are very encouraging. For the famous Deutsch’s difficult example

the algorithm obtains 18 tracks solution.

关键词

Keywords

references

Views

下载量

CSCD

Alert me when the article has been cited

提交

Tools

Publicity Resources

Review on Technology of Placement and Routing for the FPGA

Simultaneous Routing and Buffer Insertion Under Fixed Buffer Locations Based on Accurate Delay Models

Yield Driven CAD of MMIC

A Method of VLSI Timing Driven Placement

Related Author

WANG Yuan

TIAN Chun-sheng

XUE Yu

DU Zhong

MA Xiao-jing

ZHOU Chong

PANG Yong-jing

ZHANG Yao-wei

Related Institution

Beijing Microelectronics Technology Institute

Department of Micro/nanoelectronics, School of Electronics Engineering and Computer Science, Peking University

ASIC and System State Key laboratory, Fudan University

Department of Computer Science and Technology, Tsinghua University

南京电子器件研究所南京 210016

⁰