A design method on the bit-level pipelined multiplier is presented in this paper. An algorithm is derived to perform both unsigned and signed multiplication. The parallel semi-systolic array architecture dramatically saves register number

while latched Domino circuitry cuts down the device count

increases speed and lowers power consumption. A 8×8 bit multipler according to this method requires less than 3000 devices and can work at the frequency greater than 100 MHz using 2 μm CMOS technology.