Design of Arbitrary Valued Sequential Logic Circuits

Chen Xiao-jin; Zhang De-long

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Design of Arbitrary Valued Sequential Logic Circuits

更新时间：2025-12-08

- Design of Arbitrary Valued Sequential Logic Circuits
- Acta Electronica Sinica Issue 2, Pages: 57-62(1990)
- 作者机构：
  
  安徽大学
- 作者简介：
- 基金信息：
- DOI：
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- Published：1990
- 稿件说明：
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[1]陈效玖,张德龙.任意值数的时序逻辑电路设计[J].电子学报,1990(02):57-62.

Chen Xiao-jin, Zhang De-long. Design of Arbitrary Valued Sequential Logic Circuits[J]. Acta Electronica Sinica, 1990, (2): 57-62.
[1]陈效玖,张德龙.任意值数的时序逻辑电路设计[J].电子学报,1990(02):57-62. DOI：

Chen Xiao-jin, Zhang De-long. Design of Arbitrary Valued Sequential Logic Circuits[J]. Acta Electronica Sinica, 1990, (2): 57-62. DOI：

摘要

本文提出了一种值数可任意扩展的多值逻辑存贮单元——DYL多值D触发器。文中将二值时序电路设计方法推广到多值逻辑系统中

运用DYL电路的线性与或门和阈门以及多值D触发器

实现了任意值数的时序逻辑电路设计。

Abstract

A MVL memory element or DYL multi-valued D-type flip-flop in which the value can be extended arbitrarily is proposed in this paper. And by using the design method of binary sequential logic circuits in MVL field

arbitrary valued sequential logic circuits can be realized with DYL linear And-Or-gates and J-gates as well as MV-D flip-flops.

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