This work studies a MOS device fabrication tachnology to form Ti polycide gate

Ti si-licide contacts on S/D regions and shallow PN junctions simultaneously. In this technology

MOSFET of good chararacteristics with very shallow S/D PN junctions can be made by a specific MOS fabrication process including As ion implantation through titanium silicide and NH3 plasma assisted thermal annealing （NPTA） process. Using the ion implanted titanium silicide as a dopant source

the dopant redistribution and the low resistivity titanium silicide formation were completed during a high temperature annealing. The depth of PN junction was 0.1μm

and the resistivity of titanium silicide was 24μΩ·cm. Finely defined self-aligned titanium silicide contacts and interconnects have been obtained using NPTA process which effectively suppresses the lateral growth of titanium silicide during Ti/Si and Ti/poly-Si solid state interaction.