A High Speed NMOS Parallel Multiplier

Mao Yu-hai

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A High Speed NMOS Parallel Multiplier

更新时间：2025-12-08

- A High Speed NMOS Parallel Multiplier
- Acta Electronica Sinica Issue 3, Pages: 1-6(1986)
- 作者机构：
  
  清华大学无线电系
- 作者简介：
- 基金信息：
- DOI：
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- Published：1986
- 稿件说明：
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[1]茅于海.一种高速NMOS并行乘法器[J].电子学报,1986(03):1-6.

Mao Yu-hai. A High Speed NMOS Parallel Multiplier[J]. Acta Electronica Sinica, 1986, (3): 1-6.
[1]茅于海.一种高速NMOS并行乘法器[J].电子学报,1986(03):1-6. DOI：

Mao Yu-hai. A High Speed NMOS Parallel Multiplier[J]. Acta Electronica Sinica, 1986, (3): 1-6. DOI：

摘要

本文提出一种高速并行乘法器的新结构。该结构中

用Wallace树来简化改进的Booth算法

并用了一种便于用NMOS器件实现的斜进位全加器。在最后一级两位相加时

采用了具有高速进位性能的Manchester型全加器来代替一般通用的具有超前进位链的全加器

并提出了一种Manchester型全加器的新线路。该乘法器

不但门的总数比改进的Booth算法乘法器的少

且速度快。此外

它的全加器阵列形状规则

特别有利于VLSI的版图设计。

Abstract

A new configuration of high speed parallel multiplier is presented. In this configuration

Wallace tree is used to simplify the modified Booth’s algorithm. Carry save adders

suitable for NMOS implementation

are used. In the last level of two bits addition

Manchester type adder with fast carry propagation is used instead of ordinary carry look -ahead adder. A new NMOS realization of Manchester adder is presented. The total gate count of this high speed parallel multiplier is less than that of the ordinary multiplier with modified Booth’s algorithm. The time of multiplicationis also reduced. Furthermore

the configuration of CSA array is much more regular. It is especially suitable for VLSI layout design.

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