A Fast Diagnosis Algorithm lor Multiple Faults in Parity Check Circuits

Xu Xing-ning

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A Fast Diagnosis Algorithm lor Multiple Faults in Parity Check Circuits

更新时间：2025-12-08

- A Fast Diagnosis Algorithm lor Multiple Faults in Parity Check Circuits
- Acta Electronica Sinica Issue 6, Pages: 19-25(1985)
- 作者机构：
  
  北京邮电学院
- 作者简介：
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- Published：1985
- 稿件说明：
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[1]徐星宁.奇偶检测电路多重故障的快速诊断算法[J].电子学报,1985(06):19-25.

Xu Xing-ning. A Fast Diagnosis Algorithm lor Multiple Faults in Parity Check Circuits[J]. Acta Electronica Sinica, 1985, (6): 19-25.
[1]徐星宁.奇偶检测电路多重故障的快速诊断算法[J].电子学报,1985(06):19-25. DOI：

Xu Xing-ning. A Fast Diagnosis Algorithm lor Multiple Faults in Parity Check Circuits[J]. Acta Electronica Sinica, 1985, (6): 19-25. DOI：

摘要

本文提出了定位奇偶检测电路多重故障的简单而有效的算法。它基于“少数位”的概念

所得的故障定位测试集是最佳的。测试序列的长度等于原始输入端数加一。文章还阐述了自动产生最佳测试集和快速定位所有故障的具体实施方法。

Abstract

A simple and efficient algorithm for locating multiple faults in parity check circuits is presented. It is based on a new concept called "Minority Bit"

and the fault location test set so obtained is optimal.The length of the test sequence is equal to the number of primary inputs plus one. The implementation of automatic generating the optimal test set and fast locating all the faults is also discussed.

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