Logic Design of Multiple Valued Logic DYL Circuits

Zheng Qi-lun; Huang Guan-guang

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Logic Design of Multiple Valued Logic DYL Circuits

更新时间：2025-12-08

- Logic Design of Multiple Valued Logic DYL Circuits
- Acta Electronica Sinica Issue 3, Pages: 19-30(1982)
- 作者机构：
  
  华南工学院
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：1982
- 稿件说明：
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[1]郑启伦,黄贯光.多值DYL电路的逻辑设计[J].电子学报,1982(03):19-30.

Zheng Qi-lun, Huang Guan-guang. Logic Design of Multiple Valued Logic DYL Circuits[J]. Acta Electronica Sinica, 1982, (3): 19-30.
[1]郑启伦,黄贯光.多值DYL电路的逻辑设计[J].电子学报,1982(03):19-30. DOI：

Zheng Qi-lun, Huang Guan-guang. Logic Design of Multiple Valued Logic DYL Circuits[J]. Acta Electronica Sinica, 1982, (3): 19-30. DOI：

摘要

本文在前文的基础上具体介绍了MV-DYL电路的各种设计方案。实验证明这些电路工作可靠

性能稳定。本文还根据MV-DYL电路的特点

提出一种高速的多值逻辑“与或”通用阵列

阐明用100个规律排列的MV-DYL“与”门可以实现二元十值逻辑运算功能。

Abstract

A new multiple valued logic circuit （MV-DYL） has now developed

which is an excellent multiple valued logic cell[3]. All logic design programs for MV-DYL circuits are presented further in this paper

and it is proved by our experiments that the operations are reliable and the properties are stable.A high-speed AND-OR universal array of multiple valued logic is proposed

and 10100 different decimal logic functions of two variables can be realized by use of 100 MV-DYL AND gates regularly arranged.

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