A Multi-Protocol SerDes Circuit for the Applications in Software Defined Interconnection System

LI Pei-jie; SHEN Jian-liang; YUAN Hong-xiao; WANG Yong-sheng; XIA Yun-fei; ZHANG Chuan-bo

doi:10.12263/DZXB.20200149

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A Multi-Protocol SerDes Circuit for the Applications in Software Defined Interconnection System

更新时间：2025-12-08

- A Multi-Protocol SerDes Circuit for the Applications in Software Defined Interconnection System
- Acta Electronica Sinica Vol. 49, Issue 4, Pages: 817-823(2021)
- 作者机构：
  
  1. 中国人民解放军战略支援部队信息工程大学,河南,郑州,450002
  2. 32125 部队,山东,济南,250100
  3. 天津市滨海新区信息技术创新中心,天津,300457
  4. 中国人民解放军战略支援部队信息工程大学,河南,郑州,450002
  5. 32125 部队,山东,济南,250100
  6. 天津市滨海新区信息技术创新中心,天津,300457
- 作者简介：
- 基金信息：
- DOI：10.12263/DZXB.20200149
  CLC： TP302
- Published：2021
- 稿件说明：
移动端阅览
LI Pei-jie, SHEN Jian-liang, YUAN Hong-xiao, et al. A Multi-Protocol SerDes Circuit for the Applications in Software Defined Interconnection System[J]. Acta Electronica Sinica, 2021, 49(4): 817-823.
DOI：

LI Pei-jie, SHEN Jian-liang, YUAN Hong-xiao, et al. A Multi-Protocol SerDes Circuit for the Applications in Software Defined Interconnection System[J]. Acta Electronica Sinica, 2021, 49(4): 817-823. DOI： 10.12263/DZXB.20200149.

摘要

为满足片上系统的柔性互连，提出一种应用于软件定义互连系统的1.0625~10.3125Gbps多协议SerDes电路结构.该电路采用统一架构实现不同协议的规范需求，通过一种1QPLL+4Lane PLL的时钟结构实现宽频点和低抖动的时钟输出，通过可编程的发送端前向反馈均衡器和接收端线性均衡器和判决反馈均衡器电路，实现最大32dB的插损补偿.测试结果表明，所设计的SerDes电路在10.3125Gbps速率下发送总抖动为21.2ps，随机抖动均方根值为633.7fs，最大功耗29.33mW/Gbps，发送端眼图和接收端抖动容限及误码率均能够满足FC-PI-4，RapidIO 3.0，10GBase-KR，1000Base-X的协议规范要求.

Abstract

In order to meet the application requirements of flexible interconnection in system on chip (SoC)

a 1.0625~10.3125Gbps multi-protocol SerDes circuit for software defined interconnection (SDI) system is proposed. The circuit uses a unified architecture to meet the requirements of different protocols. A 1×QPLL+4×Lane PLL structure is implemented to achieve the broadband data rate and the low jitter output. The 32dB channel loss compensation is achieved by programmable feed forward equalizer (FFE)

continuous time linear equalizer (CTLE) and decision feedback equalizer (DFE) circuits. The output measures 21.2ps total jitter (TJ) and 633.7fs random jitter (RJ) RMS. The power efficiency of the test chip is 29.33mW/Gbps at 10.3125 Gbps. The output eye pattern of the transmitter

the jitter tolerance and the bit error rate of the receiver can meet the protocol specifications of FC-PI-4

RapidIO 3.0

10GBase-KR and 1000Base-X.

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