Design of Triple-Node-Upset Self-Recovery Latch in 32nm CMOS Technology

HUANG Zheng-feng; PAN Shang-jie; CAO Jian-fei; SONG Tai; OUYANG Yi-ming; LIANG Hua-guo; NI Tian-ming; LU Ying-chun

doi:10.12263/DZXB.20200530

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Design of Triple-Node-Upset Self-Recovery Latch in 32nm CMOS Technology

更新时间：2025-12-08

- Design of Triple-Node-Upset Self-Recovery Latch in 32nm CMOS Technology
- Acta Electronica Sinica Vol. 49, Issue 2, Pages: 394-400(2021)
- 作者机构：
  
  1. 合肥工业大学电子科学与应用物理学院,安徽,合肥,230601
  2. 合肥工业大学计算机与信息学院,安徽,合肥,230601
  3. 安徽工程大学电气工程学院,安徽,芜湖,241000
  4. 合肥工业大学电子科学与应用物理学院,安徽,合肥,230601
  5. 合肥工业大学计算机与信息学院,安徽,合肥,230601
  6. 安徽工程大学电气工程学院,安徽,芜湖,241000
- 作者简介：
- 基金信息：
  
  National Natural Science Foundation of China (No.61874156, No.61874157, No.61904001);Natural Science Foundation of Anhui Province (No.1908085QF272)
- DOI：10.12263/DZXB.20200530
  CLC： TN43
- Published Online：25 February 2021，
  
  Published：2021
- 稿件说明：
移动端阅览
HUANG Zheng-feng, PAN Shang-jie, CAO Jian-fei, et al. Design of Triple-Node-Upset Self-Recovery Latch in 32nm CMOS Technology[J]. Acta Electronica Sinica, 2021, 49(2): 394-400.
DOI：

HUANG Zheng-feng, PAN Shang-jie, CAO Jian-fei, et al. Design of Triple-Node-Upset Self-Recovery Latch in 32nm CMOS Technology[J]. Acta Electronica Sinica, 2021, 49(2): 394-400. DOI： 10.12263/DZXB.20200530.

摘要

CMOS工艺的特征尺寸不断缩减，电荷共享效应诱发的单粒子三点翻转成为研究热点.本文提出了一种单粒子三点翻转自恢复的抗辐射加固锁存器：Hydra-DICE（Dual Interlocked Storage Cell）.该锁存器基于24个同构的交叉耦合单元（Cross-Coupled Elements，CCE）排列成阵列结构.当内部任意三个节点同时发生单粒子翻转时，该锁存器都可以自行恢复到正确的逻辑值.与具有等效三点自恢复能力的TNURL（Triple Node Upset Self-Recoverable Latch）锁存器相比，该Hydra-DICE锁存器面积开销降低50%，延迟降低48.28%，功耗降低25%，功耗延迟积降低61.21%.仿真结果表明，该加固锁存器在容错性能、面积开销、延迟和功耗方面取得了很好的折中.

Abstract

The feature size of CMOS technology is continuously shrinking

and the single event triple-node-upset induced by the charge sharing effect has become a research hotspot. This paper proposed a single event triple-node-upset self-recovery radiation-hardened latch: Hydra-DICE. The latch is arranged in an array structure based on 24 homogeneous cross-coupled elements (CCE). When a single event upset occurs at any three internal nodes concurrently

Hydra-DICE can realize the function of self-recovery to the correct logical value. Compared with the TNURL latch which has the equivalent triple-node-upset self-recovery capability

the Hydra-DICE latch has a 50% reduction in area overhead

a 48.28% reduction in delay

a 25.00% reduction in power consumption

and a 61.21% reduction in power consumption delay product. The simulation results show that the hardened latch has made a good compromise in fault tolerance performance

area overhead

delay and power.

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