Design and Implementation of Embedded Multiple-ISA Processor Based on RISC-V

CHENG Yuan-hu; HUANG Li-bo; CUI Yi-jun; MA Sheng; WANG Yong-wen; SUI Bing-cai

doi:10.12263/DZXB.20201350

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Design and Implementation of Embedded Multiple-ISA Processor Based on RISC-V

PAPERS | 更新时间：2025-12-08

- Design and Implementation of Embedded Multiple-ISA Processor Based on RISC-V
- ACTA ELECTRONICA SINICA Vol. 49, Issue 11, Pages: 2081-2089(2021)
- 作者机构：
  
  国防科技大学计算机学院，湖南长沙 410073
- 作者简介：
- 基金信息：
- DOI：10.12263/DZXB.20201350
  CLC： TP302;
- Received：30 November 2020，
  
  Revised：2021-03-03，
  
  Published：25 November 2021
- 稿件说明：
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成元虎,黄立波,崔益俊等.基于RISC-V的嵌入式多指令集处理器设计及实现[J].电子学报,2021,49(11):2081-2089.

CHENG Yuan-hu,HUANG Li-bo,CUI Yi-jun,et al.Design and Implementation of Embedded Multiple-ISA Processor Based on RISC-V[J].ACTA ELECTRONICA SINICA,2021,49(11):2081-2089.
成元虎,黄立波,崔益俊等.基于RISC-V的嵌入式多指令集处理器设计及实现[J].电子学报,2021,49(11):2081-2089. DOI： 10.12263/DZXB.20201350.

CHENG Yuan-hu,HUANG Li-bo,CUI Yi-jun,et al.Design and Implementation of Embedded Multiple-ISA Processor Based on RISC-V[J].ACTA ELECTRONICA SINICA,2021,49(11):2081-2089. DOI： 10.12263/DZXB.20201350.

摘要

软件生态是限制RISC-V指令集架构发展的主要因素之一.让RISC-V处理器可以直接运行ARM Thumb二进制代码能在一定程度上缓解其在嵌入式领域中的软件生态问题.本文基于二进制翻译，通过硬件支持ARM Thumb的标志位、分支指令、条件执行，在RISC-V处理器上以较低的面积和功耗开销实现了对ARM Thumb程序的支持并获得了较好的性能.通过运行Embench基准程序套件，该处理器翻译运行ARM Thumb程序的平均性能能够到达直接运行RISC-V程序性能的75.5%.相较于仅使用二进制翻译支持ARM Thumb，该处理器运行ARM Thumb程序的性能提升了3.1倍，面积开销则下降了7.8%.

Abstract

Software ecology is one of the most critical factors restricting the development of RISC-V instruction set architecture. Allowing the RISC-V processor to directly run the ARM Thumb binary code can solve its software ecological problem in the embedded field to a certain extent. Based on the binary translation

this article realizes support for the ARM Thumb program and achieves comparable performance on the RISC-V processor with the lower area and power consumption overhead by using hardware to optimize ARM Thumb flag bits

branch instructions

and conditional execution. For the Embench benchmark suite

the average performance of the processor running ARM Thumb programs can reach 75.5% of directly running RISC-V programs. Compared with using only binary translation to support ARM Thumb

hardware optimization performance is improved by 3.1 times and hardware overhead is reduced by 7.8%.

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references

Sites R L , Chernoff A , Kirk M B , et al . Binary translation [J]. Communications of the ACM , 1993 , 36 ( 2 ): 69 － 81 .

Apple Inc . About the Rosetta Translation Environment [EB/OL]. https://developer.apple.com/documentation/apple_silicon/about_the_rosetta_translation_environment https://developer.apple.com/documentation/apple_silicon/about_the_rosetta_translation_environment , 2020 .

Chernoff A , Herdeg M , Hookway R , et al . FX!32: A profile-directed binary translator [J]. IEEE Micro , 1998 , 18 ( 2 ): 56 － 64 .

Bellard F. QEMU , a fast and portable dynamic translator [A]. Proceedings of the FREENIX Track: 2005 USENIX Annual Technical Conference [C]. Anaheim, CA, USA : USENIX , 2005 . 46 .

Hong D Y , Hsu C C , Yew P C , et al . HQEMU: a multi-threaded and retargetable dynamic binary translator on multicores [A]. Proceedings of the Tenth International Symposium on Code Generation and Optimization [C]. San Jose, New York : ACM , 2012 . 104 － 113 .

Altman E R , Kaeli D . Welcome to the opportunities of binary translation [J]. Computer , 2000 , 33 ( 3 ): 40 － 45 .

Shen B Y , Chen J Y , Hsu W C , et al . LLBT: an LLVM-based static binary translator [A]. Proceedings of the 2012 International Conference on Compilers , Architectures and Synthesis for Embedded Systems[C]. New York : ACM , 2012 . 51 － 60 .

Krishnan Sivaram , Debbage Mark , Ziesler Sebastian H , Roy Kanad , Sturges Andrew C , Biswas Prasenjit . Processor Architecture for Executing Two Different Fixed-length Instruction Sets [P]. US : US2005262329 , 2005-11-24 .

Fajardo J , Rutzig M B , Carro L , et al . Towards a multiple-ISA embedded system [J]. Journal of Systems Architecture the Euromicro Journal , 2013 , 59 ( 2 ): 103 － 119 .

Goetz John W , Mahin Stephen W , Bergkvist John J . Processor Capable of Supporting Two Distinct Instruction Set Architectures [P]. EP : EP0747808 , 1996-12-11 .

James Walter Rymarczyk , Michael Ignatowski , Jr Thomas J Heller . Multiple-core Processor Supporting Multiple Instruction Set Architectures [P]. US : US8806182 , 2014-08-12 .

Venkat A , Tullsen D M . Harnessing ISA diversity: design of a heterogeneous-ISA chip multiprocessor [A]. 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA) [C]. AvenueMinneapolis, MN, USA : IEEE , 2014 . 121 － 132 .

Balkind J , Lim K , Schaffner M , et al . BYOC: a" bring your own core" framework for heterogeneous-ISA research [A]. Proceedings of the Twenty-fifth International Conference on Architectural Support for Programming Languages and Operating Systems [C]. New York : ACM , 2020 . 699 － 714 .

Capella F M , Brandalero M , Carro L , et al . A multiple-ISA reconfigurable architecture [J]. Design Automation for Embedded Systems , 2015 , 19 ( 4 ): 329 － 344 .

Schiavone P D , Conti F , Rossi D , et al . Slow and steady wins the race? a comparison of ultra-low-power risc-v cores for internet-of-things applications [A]. 2017 27th International Symposium on Power and Timing Modeling , Optimization and Simulation (PATMOS)[C] . Thessaloniki, Greece : IEEE , 2017 . 1 － 8 .

Smith J , Nair R . Virtual Machines: Versatile Platforms for Systems and Processes [M]. Amsterdam : Elsevier , 2005 .

Andrew Waterman , Krste Asanovi . The RISC-V Instruction Set Manual Volume I: Unprivileged ISA [EB/OL]. https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf , 2019 .

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