Design and Application of Full Adder in Single Flux Quantum Circuits

YANG Ruo-ting; REN Jie; GAO Xiao-ping; WANG Zhen

doi:10.12263/DZXB.20210014

您当前的位置：

首页 >

文章列表页 >

Design and Application of Full Adder in Single Flux Quantum Circuits

PAPERS | 更新时间：2025-12-08

- Design and Application of Full Adder in Single Flux Quantum Circuits
- ACTA ELECTRONICA SINICA Vol. 51, Issue 2, Pages: 307-313(2023)
- 作者机构：
  
  1.中国科学院上海微系统与信息技术研究所信息功能材料国家重点实验室，上海 200050
  2.中国科学院超导电子学卓越创新中心，上海 200050
  3.中国科学院大学，北京 100049
- 作者简介：
- 基金信息：
- DOI：10.12263/DZXB.20210014
  CLC： TP331.2;
- Received：22 December 2020，
  
  Revised：2021-04-29，
  
  Published：25 February 2023
- 稿件说明：
移动端阅览
杨若婷,任洁,高小平等.超导单磁通量子数字电路的全加器设计与应用探索[J].电子学报,2023,51(02):307-313.

YANG Ruo-ting,REN Jie,GAO Xiao-ping,et al.Design and Application of Full Adder in Single Flux Quantum Circuits[J].ACTA ELECTRONICA SINICA,2023,51(02):307-313.
杨若婷,任洁,高小平等.超导单磁通量子数字电路的全加器设计与应用探索[J].电子学报,2023,51(02):307-313. DOI： 10.12263/DZXB.20210014.

YANG Ruo-ting,REN Jie,GAO Xiao-ping,et al.Design and Application of Full Adder in Single Flux Quantum Circuits[J].ACTA ELECTRONICA SINICA,2023,51(02):307-313. DOI： 10.12263/DZXB.20210014.

摘要

随着超导单磁通量子（Single Flux Quantum，SFQ）数字电路的集成度规模不断提升，基于SFQ标准单元库及知识产权（Intellectual Property，IP）电路的设计将会逐渐取代原有的专用定制化数字电路设计的方式.与此同时，IP电路也可以作为新设计方法研究和新工艺及单元库可靠性的验证电路.本文选择大规模数字电路中的基础运算单元全加器为研究对象，希望能在尚在开发中的工艺下得到一个更加稳定工作和完整测试功能的全加器.本文基于自研SIMIT Nb03工艺上开发的SFQ单元库，设计了两种类型的全加器，且实现了全加器逻辑功能和工作性能的低频与高频测试表征.本文的第二种单级型全加器跟同类型的其他全加器相比，在保证了结数量和面积消耗偏小的优势下，又减少了设计难度和便于灵活扩展，使得其在电路IP化使用中也具有指导意义.低频测试结果表明，两种全加器均正确工作，其中单级型全加器具备良好的工作阈值.该款全加器的高频测试显示电路最高工作频率可达22 GHz.本文对测试结果进行详细分析，并基于此针对大规模电路实现开展简单应用探索.

Abstract

With the increase of integration of SFQ (Single Flux Quantum) digital circuits

large scale SFQ circuits design flow based on standard cell library and IP (Intellectual Property) is gradually replacing the full custom flow that is widely used in ASIC design. Meanwhile

IP circuits are also playing important roles in robustness verification of cell library of new fabrication process as benchmark circuits. As one of the most fundamental arithmetic elements

full adder (FA) is considered to be a significant IP that provides some guidelines for large scale circuits’ design

and we hope to design a stable working FA with complete correct test function under our developing fabrication process. In this paper

we have demonstrated two kinds of FA using our SIMIT Nb03 cell library

and tested their logic function and working performance under both low and high frequency clock. Compared to other FAs of the same type

our single-stage FA reduces the design difficulty and is flexible to expand while keeping the advantages of less junctions and smaller area consumption

making it instructive in IP usage. Our two FAs have tested correct function under low frequency clock

and the single-stage FA has wide working margin. The high frequency test results indicate that the single-stage FA is able to work up to 22GHz clock frequency. Whereafter

analysis of test results is discussed

and the application exploration of large-scale circuits is carried out in the last.

关键词

Keywords

references

LIKHAREV K K , SEMENOV V K . RSFQ logic/memory family: A new Josephson-junction technology for sub-terahertz-clock-frequency digital systems [J]. IEEE Transactions on Applied Superconductivity , 1991 , 1 ( 1 ): 3 - 28 .

AKAHORI A , TANAKA M , SEKIYA A , et al . Design and demonstration of SFQ pipelined multiplier [J]. IEEE Transactions on Applied Superconductivity , 2003 , 13 ( 2 ): 559 - 562 .

OBATA K , TANAKA M , TASHIRO Y , et al . Single-flux-quantum integer multiplier with systolic array structure [J]. Physica C: Superconductivity and Its Applications , 2006 , 445-448 : 1014 - 1019 .

SAKASHITA Y , YAMANASHI Y , YOSHIKAWA N . High-speed operation of an SFQ butterfly processing circuit for FFT processors using the 10 kA/cm2 Nb process [J]. IEEE Transactions on Applied Superconductivity , 2015 , 25 ( 3 ): 1 - 5 .

KAWASAKI K , YODA K , YOSHIKAWA N , et al . Design and implementation of a high-speed bit-serial SFQ adder based on the binary decision diagram [J]. Superconductor Science & Technology , 2003 , 16 ( 12 ): 1497 - 1502 .

NAKAMOTO R , SAKURABA S , ONOMI T , et al . 4-bit SFQ multiplier based on booth encoder [J]. IEEE Transactions on Applied Superconductivity , 2011 , 21 ( 3 ): 852 - 855 .

TANAKA M , AKAIKE H , FUJIMAKI A , et al . 100-GHz single-flux-quantum bit-serial adder based on 10-niobium process [J]. IEEE Transactions on Applied Superconductivity , 2011 , 21 ( 3 ): 792 - 796 .

KATO T , YAMANASHI Y , YOSHIKAWA N , et al . 60-GHz demonstration of an SFQ half-precision bit-serial floating-point adder using 10 kA/cm(2) Nb process [C]// Proceedings of the 2013 IEEE International Superconductive Electronics Conference (ISEC) . Cambridge : IEEE , 2013 : 1 - 3 .

KIRICHENKO A , MUKHANOV O . Implementation of novel “push-forward” RSFQ carry-save serial adders [J]. IEEE Transactions on Applied Superconductivity , 1995 , 5 ( 2 ): 3010 - 3013 .

YING L , ZHANG X , NIU M , et al . Development of multi-layer fabrication process for SFQ large scale integrated digital circuits [J]. IEEE Transactions on Applied Superconductivity , 2021 , 31 ( 5 ): 1 - 4 .

ZHANG X , YING L , NIU M , et al . Process Control monitoring for fabrication technology of superconducting integrated circuits [J]. IEEE Transactions on Applied Superconductivity , 2021 , 31 ( 5 ): 1 - 6 .

GAO X , QIAO Q , WANG M , et al . Design and verification of SFQ cell library for superconducting LSI digital circuits [J]. IEEE Transactions on Applied Superconductivity , 2021 , 31 ( 5 ) : 1 - 5 .

KATAM N K , PEDRAM M . Logic optimization, complex cell design, and retiming of single flux quantum circuits [J]. IEEE Transactions on Applied Superconductivity , 2018 , 28 ( 7 ): 1 - 9 .

GAJ K , FRIEDMAN E G , FELDMAN M J . Timing of multi-gigahertz rapid single flux quantum digital circuits [J]. Journal of VLSI Signal Processing Systems , 1997 , 16 : 247 - 276 .

POLONSKY S , SHEVCHENKO P , KIRICHENKO A , et al . PSCAN'96: new software for simulation and optimization of complex RSFQ circuits [J]. IEEE Transactions on Applied Superconductivity , 1997 , 7 ( 2 ): 2685 - 2689 .

DENG Z J , YOSHIKAWA N , WHITELEY S R , et al . Data-driven self-timed RSFQ digital integrated circuit and system [J]. IEEE Transactions on Applied Superconductivity , 1997 , 7 ( 2 ): 3634 - 3637 .

CONG H , KATAM N K , PEDRAM M . Design of an SFQ full adder as a single-stage gate [C]// Proceedings of the 2019 IEEE International Superconductive Electronics Conference (ISEC) . Riverside : IEEE , 2019 : 1 - 3 .

MUKHANOV O . Design and test of RSFQ full adder [C]// Proceeding of the 4th International Superconductive Electronics Conference (ISEC) . Boulder : IEEE , 1993 : 2 - 5 .

Views

下载量

CSCD

Alert me when the article has been cited

提交

Tools

Publicity Resources

Design of n-bit Full Adder Based on Quantum-Dot Cellular Automata

Universal Design Method for Current-Mode CMOS Adders Based on Threshold-Controllable Technique

The Design and Application of QCA Full Adder Based on Improved Five-Input Majority Gate

The Design of Quantum Ternary Full Adder

Related Author

Jie REN

Xiao-Ping GAO

Zhen Wang

Ruo-Ting YANG

ZHANG Yong-qiang

XIE Guang-jun

ZHANG Hui

HANG Guo-qiang

Related Institution

CAS Center for Excellence in Superconducting Electronics （CENSE）

State Key Laboratory of Functional Materials for Informatics， Shanghai Institute of Microsystem and Information Technology （SIMIT）， Chinese Academy of Sciences

School of Microelectronics，Hefei University of Technology

浙江大学信息与电子工程学系浙江杭州

浙江大学信息与电子工程学系

⁰