Implementation of RTL Scalable High-Performance Data Compression Method

CHEN Xiao-jie; LI Bin; ZHOU Qing-lei

doi:10.12263/DZXB.20210448

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Implementation of RTL Scalable High-Performance Data Compression Method

PAPERS | 更新时间：2025-12-08

- Implementation of RTL Scalable High-Performance Data Compression Method
- ACTA ELECTRONICA SINICA Vol. 50, Issue 7, Pages: 1548-1557(2022)
- 作者机构：
  
  1.数学工程与先进计算国家重点实验室，河南郑州 450001
  2.郑州大学计算机与人工智能学院, 河南郑州 450001
- 作者简介：
- 基金信息：
- DOI：10.12263/DZXB.20210448
  CLC： TP391
- Received：07 April 2021，
  
  Revised：2022-04-09，
  
  Published：25 July 2022
- 稿件说明：
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陈晓杰,李斌,周清雷.RTL级可扩展高性能数据压缩方法实现[J].电子学报,2022,50(07):1548-1557.

CHEN Xiao-jie,LI Bin,ZHOU Qing-lei.Implementation of RTL Scalable High-Performance Data Compression Method[J].ACTA ELECTRONICA SINICA,2022,50(07):1548-1557.
陈晓杰,李斌,周清雷.RTL级可扩展高性能数据压缩方法实现[J].电子学报,2022,50(07):1548-1557. DOI： 10.12263/DZXB.20210448.

CHEN Xiao-jie,LI Bin,ZHOU Qing-lei.Implementation of RTL Scalable High-Performance Data Compression Method[J].ACTA ELECTRONICA SINICA,2022,50(07):1548-1557. DOI： 10.12263/DZXB.20210448.

摘要

针对传统的数据压缩实现方法处理性能较低，难以满足高速网络高负载、低能耗要求，本文提出了基于FPGA（Field-Programmable Gate Array）的高性能数据压缩方法.在数据计算方面，定制化一种专用并行数据匹配方法，并对压缩算法进行子任务划分，设计细粒度的串/并混合结构实现数据压缩和数据编码；在数据存储方面，设计了面向硬件的专用高效字典处理，并采用多级缓存机制优化访存结构；基于FPGA的资源面积，设计了多通道、可扩展数据压缩结构，并采用轮询策略实现多通道的数据分配和回收；在优化过程中，采用RTL（Register Transfer Level）实现数据压缩算法.实验结果表明优化后的压缩算法与CPU相比达到了1.634的加速比，吞吐量为4.33 Gb/s.

Abstract

As the low processing performance makes traditional data compression implementation methods difficult to meet the high load and low energy consumption requirements of high-speed networks

a high-performance data compression method based on field-programmable gate array is proposed. In terms of data calculation

this paper customize a dedicated parallel data matching method

divide the compression algorithm into sub-tasks

and design a fine-grained serial/parallel hybrid structure to achieve data compression and data encoding. In terms of data storage

a dedicated and efficient dictionary processing for hardware is designed

and a multi-level cache mechanism is used to optimize the memory access structure. Based on the resource area of FPGA

a multi-channel

scalable data compression structure is designed

and a polling strategy is used to realize multi-channel data allocation and recovery. In the optimization process

register transfer level is used to realize the data compression algorithm. The experimental results show that the optimized compression algorithm achieves a speedup ratio of 1.634 compared with the CPU

with a throughput of 4.33 Gb/s.

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references

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