A Quantification Method of Convolutional Neural Network Based on Data Standard Deviation

HUANG Yun; ZHANG Fan; GUO Wei; CHEN Li; YANG Guang

doi:10.12263/DZXB.20210691

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A Quantification Method of Convolutional Neural Network Based on Data Standard Deviation

PAPERS | 更新时间：2025-12-08

- A Quantification Method of Convolutional Neural Network Based on Data Standard Deviation
- ACTA ELECTRONICA SINICA Vol. 51, Issue 3, Pages: 639-647(2023)
- 作者机构：
  
  1.信息工程大学, 河南郑州 450001
  2.国家数字交换系统工程技术研究中心, 河南郑州 450002
  3.河南省广播电视监测中心, 河南郑州 450002
- 作者简介：
- 基金信息：
  
  Foundation for Innovative Research Groups of the National Natural Science Foundation of China(61521003)
- DOI：10.12263/DZXB.20210691
  CLC： TP391
- Received：29 May 2021，
  
  Revised：2021-10-18，
  
  Published：25 March 2023
- 稿件说明：
移动端阅览
黄赟,张帆,郭威等.一种基于数据标准差的卷积神经网络量化方法[J].电子学报,2023,51(03):639-647.

HUANG Yun,ZHANG Fan,GUO Wei,et al.A Quantification Method of Convolutional Neural Network Based on Data Standard Deviation[J].ACTA ELECTRONICA SINICA,2023,51(03):639-647.
黄赟,张帆,郭威等.一种基于数据标准差的卷积神经网络量化方法[J].电子学报,2023,51(03):639-647. DOI： 10.12263/DZXB.20210691.

HUANG Yun,ZHANG Fan,GUO Wei,et al.A Quantification Method of Convolutional Neural Network Based on Data Standard Deviation[J].ACTA ELECTRONICA SINICA,2023,51(03):639-647. DOI： 10.12263/DZXB.20210691.

摘要

当前卷积神经网络模型存在规模过大且运算复杂的问题，难以应用部署在资源受限的计算平台. 针对此问题，本文基于数据标准差提出了一种适合部署在现场可编程门阵列（Field Programmable Gate Array， FPGA）上的对数量化方法. 首先，依据FPGA的特性提出对数量化方法，将32 bit浮点乘法运算转换为整数乘法及移位运算，提高了运算效率. 然后通过研究数据分布特点，提出基于数据标准差的输入量化及权值混合bit量化方法，能够有效减少量化损失. 通过对RepVGG、EfficientNet等网络进行效率与精度对比实验，8 bit量化使得大型神经网络精度仅下降1%左右；输入量化为8 bit，权重量化为10 bit场景下，模型精度损失小于0.2%，达到浮点模型几乎相同的准确率. 实验表明，所提量化方法能够使得模型大小减少75%左右，在基本保持原有模型准确率的同时有效地降低功耗损失、提高运算效率.

Abstract

Due to the large scale of the current convolutional neural network model and complex calculations

it is not suitable for deployment on resource-constrained computing platforms. In order to solve this problem

this paper proposes a logarithmic quantization method based on data standard deviation

which is suitable for deployment on FPGA (Field Programmable Gate Array). According to the characteristics of FPGA

this paper proposes a logarithmic quantization method to convert the 32 bit floating point multiplication operation into integer multiplication and shift operation

which improves the efficiency of the operation. By studying the characteristics of data distribution

the input quantization and mixed bit weight quantization methods based on data standard deviation are proposed

which can effectively reduce the quantization loss. The experimental results show that the accuracy of large-scale neural network is only reduced by about 1% due to 8-bit quantization. When the input is quantized to 8 bits and the weight is quantized to 10 bits

the accuracy loss of the model is less than 0.2%

which is almost the same as that of the floating-point model. Experimental results show that the proposed method can reduce the size of the model by about 75%

and effectively reduce the power loss and improve the computing efficiency while maintaining the accuracy of the original model.

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references

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