A Hardware Design of ZUC-256 Stream Cipher of Pipelining Structure with High Throughput

LIU Yun-tao; SHEN Ze-sheng; FANG Shuo; WANG Yun

doi:10.12263/DZXB.20211327

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A Hardware Design of ZUC-256 Stream Cipher of Pipelining Structure with High Throughput

PAPERS | 更新时间：2025-12-08

- A Hardware Design of ZUC-256 Stream Cipher of Pipelining Structure with High Throughput
- ACTA ELECTRONICA SINICA Vol. 51, Issue 2, Pages: 438-445(2023)
- 作者机构：
  
  1.哈尔滨工程大学信息与通信工程学院，黑龙江哈尔滨 150001
  2.先进船舶通信与信息技术工业和信息化部重点实验室，黑龙江哈尔滨 150001
  3.广东省大湾区集成电路与系统应用研究院，广东广州 510535
- 作者简介：
- 基金信息：
  
  National Natural Science Foundation of Heilongjiang Province(JJ2018ZR1021);Fundamental Research Funds for the Central Universities(3072021CF0806)
- DOI：10.12263/DZXB.20211327
  CLC： TN431.2;
- Received：28 September 2021，
  
  Revised：2022-05-01，
  
  Published：25 February 2023
- 稿件说明：
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刘云涛,申泽生,方硕等.高吞吐率流水线结构的ZUC-256流密码硬件设计[J].电子学报,2023,51(02):438-445.

LIU Yun-tao,SHEN Ze-sheng,FANG Shuo,et al.A Hardware Design of ZUC-256 Stream Cipher of Pipelining Structure with High Throughput[J].ACTA ELECTRONICA SINICA,2023,51(02):438-445.
刘云涛,申泽生,方硕等.高吞吐率流水线结构的ZUC-256流密码硬件设计[J].电子学报,2023,51(02):438-445. DOI： 10.12263/DZXB.20211327.

LIU Yun-tao,SHEN Ze-sheng,FANG Shuo,et al.A Hardware Design of ZUC-256 Stream Cipher of Pipelining Structure with High Throughput[J].ACTA ELECTRONICA SINICA,2023,51(02):438-445. DOI： 10.12263/DZXB.20211327.

摘要

ZUC-256是为提供5G应用环境256 bit安全性而设计的流密码算法，数据处理速率是其核心性能之一，为此本文提出一种具有高吞吐率特性的硬件设计方案.该方案采用流水线拆分关键路径初步提升系统工作频率，并提出一种完成模（

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）加算法的优化电路进一步缩短关键路径延迟，该模加结构相较于现有结构缩短了42%的逻辑延迟，能够显著提升系统工作频率和吞吐率.本研究分别采用Xilinx公司的Virtex-5器件、Alter公司的DE2-115器件和TSMC 90 nm工艺实现了该流密码硬件结构.实验测试结果表明，采用TSMC 90 nm工艺实现的ASIC系统工作频率最高达到1200 MHz，吞吐率可达38.4 Gbps，比现有研究成果提升71%.

Abstract

ZUC-256 is a stream cipher algorithm designed to provide 256-bit security in a 5G application environment. The data processing rate is one of ZUC-256 core performances. Therefore

a hardware design scheme with high throughput characteristics is proposed. This scheme uses pipeline to split the critical path to increase the operating frequency of the system

and proposes an optimized circuit that completes the modular(

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7.53533268

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) addition algorithm to further shorten the critical path delay. Compared with the conventional structure

the modular addition structure can shorten the path delay by 42%

which can significantly improve the working frequency and throughput rate of the system. This research implements the structure based on Xilinx's Virtex-5 device

Alter's DE2-115 device and TSMC 90 nm technology respectively. The experimental results shows that the ASCI system implemented by TSMC 90 nm technology achieves the maximum operating frequency of 1200 MHz

and the throughput rate can reach 38.4 Gbps

which is 71% higher than the existing research results.

关键词

Keywords

references

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