Research on Self-Accelerated Establishment Method of Column Bus for Super Large Array CMOS Image Sensor

GUO Zhong-jie; CHENG Xin-qi; YU Ning-mei; XU Rui-ming; LI Chen; SU Chang-xu

doi:10.12263/DZXB.20220002

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Research on Self-Accelerated Establishment Method of Column Bus for Super Large Array CMOS Image Sensor

PAPERS | 更新时间：2025-12-08

- Research on Self-Accelerated Establishment Method of Column Bus for Super Large Array CMOS Image Sensor
- ACTA ELECTRONICA SINICA Vol. 51, Issue 6, Pages: 1581-1589(2023)
- 作者机构：
  
  西安理工大学自动化与信息工程学院，陕西西安 710048
- 作者简介：
- 基金信息：
  
  Key Research and Development Plan Projects in Shaanxi Province(2021GY-060);Shaanxi Provincial Innovation Capability Support Program Project(2022TD-39)
- DOI：10.12263/DZXB.20220002
  CLC： TN47;
- Received：27 December 2021，
  
  Revised：2022-07-04，
  
  Published：25 June 2023
- 稿件说明：
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郭仲杰,程新齐,余宁梅等.面向超大面阵CMOS图像传感器的列总线自加速建立方法研究[J].电子学报,2023,51(06):1581-1589.

GUO Zhong-jie,CHENG Xin-qi,YU Ning-mei,et al.Research on Self-Accelerated Establishment Method of Column Bus for Super Large Array CMOS Image Sensor[J].ACTA ELECTRONICA SINICA,2023,51(06):1581-1589.
郭仲杰,程新齐,余宁梅等.面向超大面阵CMOS图像传感器的列总线自加速建立方法研究[J].电子学报,2023,51(06):1581-1589. DOI： 10.12263/DZXB.20220002.

GUO Zhong-jie,CHENG Xin-qi,YU Ning-mei,et al.Research on Self-Accelerated Establishment Method of Column Bus for Super Large Array CMOS Image Sensor[J].ACTA ELECTRONICA SINICA,2023,51(06):1581-1589. DOI： 10.12263/DZXB.20220002.

摘要

在超大面阵CMOS图像传感器（COMS Image Sensor，CIS）中，由于像素面阵输出的列总线上存在超大的寄生电阻电容，列总线信号建立速度的主导因素发生改变，严重影响了读出速度.为了解决这一问题，本文提出了一种可应用于超大面阵CIS列并行读出机制的列总线自加速建立方法，基于电流增益增强理论，在不引入额外总线的前提下，通过对模拟信号建立过程的实时跟踪，加快列总线信号的变化过程，在列总线终端实现了自加速，将超长列总线的读出速度提升了一个数量级.55 nm工艺下的测试与实验结果显示，采用本文提出的方法后，在亿级像素规模CIS列总线引入的寄生电容与寄生电阻分别为47 pF和20 kΩ的情况下，光电信号从像素节点到列级电路采样节点的上升建立时间由4 μs缩短至790 ns，下降建立时间由22.43 μs缩短至1.17 μs，将亿级像素规模的CMOS图像传感器帧频提升至100帧，压缩了相关双采样的取样间隔时间，从而拓宽了噪声抑制的频率范围.本文方法实现了在保持低噪声和高速读出的同时，单列功耗仅有6.6 μW.

Abstract

In the super large array CMOS image sensor (CIS)

due to the large parasitic resistance and capacitance on the column bus output by pixel area array

the dominant factor of column bus signal establishment speed is changed

which seriously affects the readout speed. In order to solve the problem

this paper proposes a high-speed readout circuit that can be applied to the very large array of column parallel readout mechanism CIS. Based on the current gain enhancement theory

on the premise of not produce extra bus

by tracking the analog signal establishment process in real time

the change process of the column bus signal is accelerated

self-acceleration is realized in the terminal of the column bus

and the reading speed of the ultra-long column bus is improved by an order of magnitude. The test and experimental results show that after using the method proposed in this paper

for the 47 pF parasitic capacitance and 20 kΩ parasitic resistance generated by the 100 million pixel CIS column bus in the 55 nm process

the rising time of the photoelectric signal from the pixel node to the column level circuit sampling node is shortened from 4 μs to 790 ns

and the falling time decreased from 22.43 μs to 1.17 μs. On the one hand

the frame rate of the multi-million-pixel CMOS image sensor is increased to 100 frames

and the sampling interval time of the relevant double sampling is compressed

so the frequency range of noise suppression is broadened. While realizing low noise and high speed readout

the single-column power consumption is only 6.6 μW.

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references

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