Research on Ultra-Low On-Resistance Trench Gate LDMOS Device

LIN Xiao-nan; WU Tuan-zhuang; XU Chao-qi; LI Ren-wei; ZHANG Yi; XUE Lu-jie; CHEN Shu-xian; LIN Feng; LIU Si-yang; SUN Wei-feng

doi:10.12263/DZXB.20220020

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Research on Ultra-Low On-Resistance Trench Gate LDMOS Device

PAPERS | 更新时间：2025-12-08

- Research on Ultra-Low On-Resistance Trench Gate LDMOS Device
- ACTA ELECTRONICA SINICA Vol. 51, Issue 8, Pages: 1995-2002(2023)
- 作者机构：
  
  1.东南大学电子科学与工程学院,江苏南京 210096
  2.东南大学微电子学院,江苏无锡 214000
  3.无锡华润上华科技有限公司,江苏无锡 214000
- 作者简介：
- 基金信息：
  
  Southeast University Zhishan Scholars Fundation(2242021R41080)
- DOI：10.12263/DZXB.20220020
  CLC： TN323+.4;
- Received：03 January 2022，
  
  Revised：2022-06-23，
  
  Published：25 August 2023
- 稿件说明：
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吝晓楠,吴团庄,许超奇等.超低导通电阻沟槽栅LDMOS器件研究[J].电子学报,2023,51(08):1995-2002.

LIN Xiao-nan,WU Tuan-zhuang,XU Chao-qi,et al.Research on Ultra-Low On-Resistance Trench Gate LDMOS Device[J].ACTA ELECTRONICA SINICA,2023,51(08):1995-2002.
吝晓楠,吴团庄,许超奇等.超低导通电阻沟槽栅LDMOS器件研究[J].电子学报,2023,51(08):1995-2002. DOI： 10.12263/DZXB.20220020.

LIN Xiao-nan,WU Tuan-zhuang,XU Chao-qi,et al.Research on Ultra-Low On-Resistance Trench Gate LDMOS Device[J].ACTA ELECTRONICA SINICA,2023,51(08):1995-2002. DOI： 10.12263/DZXB.20220020.

摘要

本文提出了一种具有超低特征导通电阻的沟槽栅横向双扩散场效应晶体管（Trench Gate Lateral Double-diffused MOSFET，TG-LDMOS）.本结构源极和漏极都在表面，与BCD（Bipolar CMOS DMOS）工艺相兼容.通过引入介质沟槽、垂直栅极、栅极下方的源极多晶硅以及栅极右侧的厚氧化层，将传统集成型功率器件的一维耐压拓宽为二维耐压，包括横向耐压与纵向耐压两个方向.其中，纵向耐压不占用横向元胞尺寸，进而在相同耐压水平上，使TG-LDMOS具有分立功率器件耐压效率高、导通电阻低的特点.本结构通过仿真优化做到了击穿电压（

）为52 V，特征导通电阻（

on，sp

）为10 mΩ·mm

.结果表明，TG-LDMOS突破了硅器件的极限关系，与硅极限相比特征导通电阻降低了48%.

Abstract

A trench gate lateral double-diffused MOSFET (TG-LDMOS) with ultra-low specific on-resistance (

) is proposed. With source and drain contact placement at the top silicon surface

our device is compatible with BCD (Bipolar CMOS DMOS) technologies. Compared with conventional integrated power devices

by introducing the dielectric trench

vertical gate

polysilicon source and thick oxide layer

one-dimensional withstand voltage is broadened to two-dimensional withstand voltage

including both lateral and vertical directions. The vertical withstand voltage doesn't occupy the lateral cell pitch

just like the discrete power devices

so that our device has the characteristics of high voltage withstand efficiency and low on-resistance at the same breakdown voltage (

). The TG-LDMOS is optimized to achieve

of 52 V and

of 10 mΩ·mm

. The simulation results show that the TG-LDMOS breaks through the silicon limit

and

is reduced by 48% compared with the silicon limit.

关键词

Keywords

references

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