High Speed Fully Parallel Two-Step ADC Design Method for Hundred Million Level CMOS Image Sensors

GUO Zhong-jie; XU Rui-ming; CHEN Xin-qi; YU Ning-mei; SU Chang-xu; LI Chen

doi:10.12263/DZXB.20220022

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High Speed Fully Parallel Two-Step ADC Design Method for Hundred Million Level CMOS Image Sensors

PAPERS | 更新时间：2025-12-08

- High Speed Fully Parallel Two-Step ADC Design Method for Hundred Million Level CMOS Image Sensors
- ACTA ELECTRONICA SINICA Vol. 51, Issue 8, Pages: 2067-2075(2023)
- 作者机构：
  
  西安理工大学自动化与信息工程学院，陕西西安 710048
- 作者简介：
- 基金信息：
  
  National Natural Science Foundation of China(62171367);Key Research and Development Plan Projects in Shaanxi Province(2021GY-060);Shaanxi Provincial Innovation Capability Support Program Project(2022TD-39)
- DOI：10.12263/DZXB.20220022
  CLC： TN47;
- Received：03 January 2022，
  
  Revised：2022-03-29，
  
  Published：25 August 2023
- 稿件说明：
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郭仲杰,许睿明,程新齐等.面向亿级CMOS图像传感器的高速全并行两步式ADC设计方法[J].电子学报,2023,51(08):2067-2075.

GUO Zhong-jie,XU Rui-ming,CHEN Xin-qi,et al.High Speed Fully Parallel Two-Step ADC Design Method for Hundred Million Level CMOS Image Sensors[J].ACTA ELECTRONICA SINICA,2023,51(08):2067-2075.
郭仲杰,许睿明,程新齐等.面向亿级CMOS图像传感器的高速全并行两步式ADC设计方法[J].电子学报,2023,51(08):2067-2075. DOI： 10.12263/DZXB.20220022.

GUO Zhong-jie,XU Rui-ming,CHEN Xin-qi,et al.High Speed Fully Parallel Two-Step ADC Design Method for Hundred Million Level CMOS Image Sensors[J].ACTA ELECTRONICA SINICA,2023,51(08):2067-2075. DOI： 10.12263/DZXB.20220022.

摘要

针对传统单斜式模数转换器（Analogue-to-Digital Conversion，ADC）和串行两步式ADC在面向大面阵CMOS图像传感器读出过程中的速度瓶颈问题，本文提出了一种用于高速CMOS图像传感器的全并行两步式ADC设计方法，该ADC设计方法基于时间共享和时间压缩思想，将细量化时间提前到粗量化时间段内，解决了传统方法的时间冗余问题；同时针对两步式结构在采样过程中的电荷注入和时钟馈通问题，提出了一种基于误差同步存储技术的误差校正方法，消除了采样电路非理想因素对ADC性能的影响.本文基于55 nm 1P4M CMOS工艺对所提方法完成了详细电路设计和全面测试验证，在模拟电压为3.3 V，数字电压为1.2 V，时钟频率为250 MHz，输入信号为1.472 V的设计条件下，本文设计实现的13 bit ADC转换时间为512 ns，DNL（Differential NonLinearity）为

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19.21933365

2.28600001

，INL（Integral NonLinearity）为

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19.55800056

2.28600001

.信噪失真比（Signal to Noise and Distortion Ratio，SNDR）达到70 dB，有效位数为11.33 bit，列级功耗为47 μW.相比现有的先进ADC，本文提出的方法在保证低功耗、高精度的同时，使ADC转换速率提高了74.4%以上，为高速高精度CMOS图像传感器的读出与量化提供了一定的理论支撑.

Abstract

Aiming at the speed bottleneck problem of traditional single-slope analog-to-digital converter (ADC) and serial two-step ADC in the readout process of large-array CMOS image sensors

this paper proposes a fully parallel two-step ADC for high speed CMOS image sensors. The ADC design method is based on the idea of time sharing and time compression

advances the fine conversion time to the coarse conversion time period

and solves the time redundancy problem of the traditional method. At the same time

aiming at the Charge Injection and Clock Feedthrough problems in the sampling process of the two-step structure

an error correction method based on the error synchronization storage technology is proposed

which eliminates the impact of the non-ideal factors of the sampling circuit on the performance of the ADC. Based on the 55 nm 1P4M CMOS process

this paper has completed the detailed circuit design and comprehensive test verification of the proposed method. Under the design conditions of analog voltage 3.3 V

digital voltage 1.2 V

clock frequency 250 MHz and input signal 1.472 V

the proposed 13-bit ADC achieves the differential nonlinearity (DNL) of +0.8/-0.8LSB and the integral nonlinearity (INL) of +2.1/-3.5LSB and Conversion time of 512 ns .The effective number of bits (ENOB) is 11.33 bit and the power consumption is 47 μW. Compared with the existing advanced ADCs

the method proposed in this paper can increase the ADC conversion rate by more than 74.4% while ensuring low power consumption and high precision

providing certain theoretical support for the readout and conversion of high-speed and high-precision CMOS image sensors.

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Keywords

references

ZHANG Q H , NING N , LI J , et al . A high area-efficiency 14-bit SAR ADC with hybrid capacitor DAC for array sensors [J ] . IEEE Transactions on Circuits and Systems I: Regular Papers , 2020 , 67 ( 12 ): 4396 - 4408 .

KAUR A , MISHRA D , SARKAR M . A 12-bit, 2.5-bit/phase column-parallel cyclic ADC [J ] . IEEE Transactions on Very Large Scale Integration(VLSI) Systems , 2019 , 27 ( 1 ): 248 - 252 .

KIM J B , HONG S K , KWON O K . A low-power CMOS image sensor with area-efficient 14-bit two-step SA ADCs using pseudomultiple sampling method [J ] . IEEE Transactions on Circuits and Systems II: Express Briefs , 2015 , 62 ( 5 ): 451 - 455 .

SEO M W , SUH S H , IIDA T , et al . A low-noise high intrascene dynamic range CMOS image sensor with a 13 to 19b variable-resolution column-parallel folding-integration/cyclic ADC [J ] . IEEE Journal of Solid-State Circuits , 2012 , 47 ( 1 ): 272 - 283 .

DEYAN L , MARTIN W , BHASKAR C . A 1-μs ramp time 12-bit column-parallel flash TDC-interpolated single-slope ADC with digital delay-element calibration [J ] . IEEE Transactions on Circuits and Systems I: Regular Papers , 2018 , 66 ( 1 ): 54 - 67 .

SHINOZUKA Y , SHIRAISHI K , FURUTA M , et al . A single-slope based low-noise ADC with input-signal-dependent multiple sampling scheme for CMOS image sensors [C ] // 2015 IEEE International Symposium on Circuits and Systems . Lisbon : IEEE , 2015 : 357 - 360 .

BAE J , KIM D , HAM S , et al . A two-step A/D conversion and column self-calibration technique for low noise CMOS image sensors [J ] . Sensors , 2014 , 14 ( 7 ): 11825 - 11843 .

LYU T , YAO S Y , NIE K M , et al . A 12-bit high-speed column-parallel two-step single-slope analog-to-digital converter (ADC) for CMOS image sensors [J ] . Sensors(Basel, Switzerland) , 2014 , 14 ( 11 ): 21603 - 21625 .

LEE J N , PARK H , SONG B , et al . High frame-rate VGA CMOS image sensor using non-memory capacitor two-step single-slope ADCs [J ] . IEEE Transactions on Circuits and Systems I: Regular Papers , 2015 , 62 ( 9 ): 2147 - 2155 .

WEI J W , LI X A , SUN L , et al . A low-power column-parallel gain-adaptive single-slope ADC for CMOS image sensors [J ] . Electronics , 2020 , 9 ( 5 ): 757 .

ZHANG Q H , NING N , LI J , et al . A 12-bit column-parallel two-step single-slope ADC with a foreground calibration for CMOS image sensors [J ] . IEEE Access , 2020 , 8 : 172467 - 172480 .

PARK H , YU C Z , KIM H , et al . Low power CMOS image sensors using two step single slope ADC with bandwidth-limited comparators & voltage range extended ramp generator for battery-limited application [J ] . IEEE Sensors Journal , 2020 , 20 ( 6 ): 2831 - 2838 .

NIE K M , ZHA W B , SHI X L , et al . A single slope ADC with row-wise noise reduction technique for CMOS image sensor [J ] . IEEE Transactions on Circuits and Systems I: Regular Papers , 2020 , 67 ( 9 ): 2873 - 2882 .

LEE J N , LEE J , BURM J . A CMOS image sensor with non-memory capacitor two-step single slope ADC for high frame rate [C ] // 2015 International SoC Design Conference (ISOCC) . Piscataway : IEEE , 2016 : 333 - 334 .

CHENG X , ZENG X Y , FENG Q . Analysis and improvement of ramp gain error in single-ramp single-slope ADCs for CMOS image sensors [J ] . Microelectronics Journal , 2016 , 58 : 23 - 31 .

唐枋 , 唐建国 . 用于CMOS图像传感器的12位低功耗单斜坡模数转换器设计 [J ] . 电子学报 , 2013 , 41 ( 2 ): 352 - 356 .

TANG F , TANG J G . 12Bit low power single slope ADC design for CMOS image sensor [J ] . Acta Electronica Sinica , 2013 , 41 ( 2 ): 352 - 356 . (in Chinese)

HUANG W J , ZHANG Q H , LI J , et al . A calibration technique for two-step single-slope analog-to-digital converter [C ] // 2019 IEEE 13th International Conference on ASIC (ASICON) . Chongqing : IEEE , 2019 : 1 - 4 .

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