Column Level ADC Design Method of CMOS Image Sensor Based on Coarse and Fine Quantization Parallel and TDC Hybrid

GUO Zhong-jie; SU Chang-xu; XU Rui-ming; CHENG Xin-qi; YU Ning-mei; LI Chen

doi:10.12263/DZXB.20220744

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Column Level ADC Design Method of CMOS Image Sensor Based on Coarse and Fine Quantization Parallel and TDC Hybrid

PAPERS | 更新时间：2025-12-11

- Column Level ADC Design Method of CMOS Image Sensor Based on Coarse and Fine Quantization Parallel and TDC Hybrid
- ACTA ELECTRONICA SINICA Vol. 52, Issue 2, Pages: 486-499(2024)
- 作者机构：
  
  西安理工大学自动化与信息工程学院，陕西西安 710048
- 作者简介：
- 基金信息：
  
  National Natural Science Foundation of China(62171367)
- DOI：10.12263/DZXB.20220744
  CLC： TN47;
- Received：28 June 2022，
  
  Revised：2023-01-18，
  
  Published：25 February 2024
- 稿件说明：
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郭仲杰,苏昌勖,许睿明,等. 基于粗细量化并行与TDC混合的CMOS图像传感器列级ADC设计方法[J]. 电子学报,2024,52(02):486-499.

GUO Zhong-jie, SU Chang-xu, XU Rui-ming, et al. Column Level ADC Design Method of CMOS Image Sensor Based on Coarse and Fine Quantization Parallel and TDC Hybrid[J]. Acta Electronica Sinica, 2024, 52(02): 486-499.
郭仲杰,苏昌勖,许睿明,等. 基于粗细量化并行与TDC混合的CMOS图像传感器列级ADC设计方法[J]. 电子学报,2024,52(02):486-499. DOI：10.12263/DZXB.20220744

GUO Zhong-jie, SU Chang-xu, XU Rui-ming, et al. Column Level ADC Design Method of CMOS Image Sensor Based on Coarse and Fine Quantization Parallel and TDC Hybrid[J]. Acta Electronica Sinica, 2024, 52(02): 486-499. DOI：10.12263/DZXB.20220744

摘要

针对传统单斜式模数转换器（Analog-to-Digital Converter，ADC）和串行两步式ADC在面向大面阵CMOS（Complementary Metal Oxide Semiconductor）图像传感器读出过程中的速度瓶颈问题，本文提出了一种用于高速CMOS图像传感器的全并行ADC设计方法．该方法基于时间共享和时间压缩思想，将细量化时间提前到粗量化时间段内，解决了传统方法的时间冗余问题；同时采用插入式时间差值TDC（Time-to-Digital Converter），实现了全局低频时钟下的快速转换机制．本文基于55-nm 1P4M CMOS工艺对所提方法完成了详细电路设计和全面测试验证，在模拟电压3.3 V，数字电压1.2 V，时钟频率250 MHz，输入电压1.2~2.7 V的情况下，将行时间压缩至825 ns，ADC的微分非线性和积分非线性分别为

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LSB，信噪失真比（Signal-to-Noise-and-Distortion Ratio，SNDR）为68.271 dB，有效位数（Effective Numbers Of Bits，ENOB）达到11.048 9 bit，列不一致性低于0.05%．相比现有的先进ADC，本文提出的方法在保证低功耗、高精度的同时，ADC转换速率提高了87.1%以上，为高速高精度CMOS图像传感器的读出与量化提供了一定的理论支撑．

Abstract

Aiming at the speed bottleneck of traditional single-slope analog-to-digital converters (ADC) and serial two-step ADC in the readout process for large area array CMOS (Complementary Metal Oxide Semiconductor) image sensors

this paper proposes a fully parallel ADC design method for high-speed CMOS image sensors. Based on the idea of time sharing and time compression

the ADC design method advances the fine quantization time to the coarse quantization time period

which solves the time redundancy problem of the traditional method; at the same time

the interpolated time difference TDC (Time-to-Digital Converter) is used to realize the global Fast transition mechanism at low frequency clocks. Based on the 55-nm 1P4M CMOS process

this paper completes the detailed circuit design and comprehensive testing and verification of the proposed method. Under the analog voltage of 3.3 V

the digital voltage of 1.2 V

the clock frequency of 250 MHz

and the input voltage range of 1.2~2.7 V

the line time is compressed to 825 ns

the differential nonlinearity and integral nonlinearity of the ADC are

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LSB and

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LSB

respectively

the signal-to-noise-distortion ratio (SNDR) is 68.271 dB

the effective number of bits (ENOB) reaches 11.049 bit

column The inconsistency is less than 0.05%. Compared with the existing advanced ADC

the method proposed in this paper can ensure the low power consumption and high precision

while the ADC conversion rate is increased by more than 87.1%. Quantification provides some theoretical support.

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Keywords

references

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