Automatic Test Pattern Solving with Fault Property Prediction

HE Li-yuan; HUANG Jun-hua; TAO Ji-ping

doi:10.12263/DZXB.20221121

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Automatic Test Pattern Solving with Fault Property Prediction

PAPERS | 更新时间：2025-12-11

- Automatic Test Pattern Solving with Fault Property Prediction
- ACTA ELECTRONICA SINICA Vol. 51, Issue 12, Pages: 3540-3548(2023)
- 作者机构：
  
  1.厦门大学自动化系，福建厦门 361102
  2.华为诺亚方舟实验室，广东深圳 518000
- 作者简介：
- 基金信息：
  
  National Natural Science Foundation of Fujian Province(2020J01053)
- DOI：10.12263/DZXB.20221121
  CLC： TN407;TP183
- Received：09 October 2022，
  
  Revised：2023-05-08，
  
  Published：25 December 2023
- 稿件说明：
移动端阅览
贺丽媛,黄俊华,陶继平.带有故障性质预测的自动测试向量求解模型[J].电子学报,2023,51(12):3540-3548.

HE Li-yuan,HUANG Jun-hua,TAO Ji-ping.Automatic Test Pattern Solving with Fault Property Prediction[J].ACTA ELECTRONICA SINICA,2023,51(12):3540-3548.
贺丽媛,黄俊华,陶继平.带有故障性质预测的自动测试向量求解模型[J].电子学报,2023,51(12):3540-3548. DOI： 10.12263/DZXB.20221121.

HE Li-yuan,HUANG Jun-hua,TAO Ji-ping.Automatic Test Pattern Solving with Fault Property Prediction[J].ACTA ELECTRONICA SINICA,2023,51(12):3540-3548. DOI： 10.12263/DZXB.20221121.

摘要

基于布尔满足模型的自动测试向量生成是芯片故障检测的关键环节，相应布尔问题的求解已然成为整个故障检测过程的效率瓶颈.本文研究了主流自动测试向量求解框架中不同算子对求解效率的影响，在保证测试向量求解流程完备性的同时引入基于深度学习的故障分析机制，并将分析结果用于算子的自动选择和初始求解状态的确定，旨在优化整体求解进程.针对因真实电路故障数据不足导致模型学习效果欠佳的问题，本文利用生成对抗网络实现数据增广，结合多层图卷积神经网络促进高效表征学习，从而提高故障性质的预测精度.在若干真实电路上的实验结果表明，本文所提出的新框架与原有框架相比，平均求解效率提升近20%.

Abstract

Automatic test pattern generation (ATPG) based on the Boolean satisfaction model plays a key part in chip fault detection flow

in which solving the corresponding Boolean satisfiability problem (SAT) becomes the efficacy bottleneck of the whole process. In this paper

the influence of different operators on the solution efficiency in the mainstream automatic test pattern solution framework is studied. While ensuring the integrity of the test pattern solution process

a fault analysis mechanism based on deep learning is introduced

and the output vectors are used for the automatic selection of operators and the determination of initial solution states so as to accelerate the overall solution process. To alleviate poor performance mainly caused by insufficient real-world circuit fault data

a generative adversarial network (GAN)

followed by a multi-layer graph convolutional neural network (GCN) which is designed to boost representation learning

is leveraged for data augmentation. Experimental results on several real circuits show that the proposed new framework

compared with the original version

has an average solution improvement of nearly 20%.

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references

HUANG J H , ZHEN H L , WANG N X , et al . Accelerate SAT-based ATPG via preprocessing and new conflict management heuristics [C ] // 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC) . New York : ACM , 2022 : 365 - 370 .

SENGUPTA A , NABEEL M , YASIN M , et al . ATPG-based cost-effective, secure logic locking [C ] // 2018 IEEE 36th VLSI Test Symposium (VTS) . Piscataway : IEEE , 2018 : 1 - 6 .

SMIRNOV K K , NAZAROV A V , BLINOV V V . Methods of designing electrical equipment for testing very large scale integrated circuit [J ] . International Journal of Nanotechnology , 2021 , 18 ( 9/10 ): 847 - 868 .

COOK S A . The complexity of theorem-proving procedures [C ] // Proceedings of the Third Annual ACM Symposium on Theory of Computing . New York : ACM , 1971 : 151 - 158 .

CHAKRADHAR S T , AGRAWAL V D . A transitive closure based algorithm for test generation [C ] // Proceedings of the 28th ACM/IEEE Design Automation Conference . New York : ACM , 1991 : 353 - 358 .

DRECHSLER R , EGGERSGLUSS S , FEY G , et al . On acceleration of SAT-based ATPG for industrial designs [J ] . IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , 2008 , 27 ( 7 ): 1329 - 1333 .

LUO M , LI C M , XIAO F , et al . An effective learnt clause minimization approach for CDCL SAT solvers [C ] // Proceedings of the 26th International Joint Conference on Artificial Intelligence . Melbourne : AAAI Press , 2017 : 703 - 711 .

LIANG J H , GANESH V , ZULKOSKI E , et al . Understanding VSIDS branching heuristics in conflict-driven clause-learning SAT solvers [C ] // Hardware and Software: Verification and Testing . Cham : Springer International Publishing , 2015 : 225 - 241 .

HEULE M J , KULLMANN O , WIERINGA S , et al . Cube and conquer: Guiding CDCL SAT solvers by lookaheads [C ] // 7th International Haifa Verification Conference . Haifa : Springer , 2012 : 50 - 65 .

STEPHAN P , BRAYTON R K , SANGIOVANNI-VINCENTELLI A L . Combinational test generation using satisfiability [J ] . IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , 1996 , 15 ( 9 ): 1167 - 1176 .

LARRABEE T . Test pattern generation using Boolean satisfiability [J ] . IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , 1992 , 11 ( 1 ): 4 - 15 .

CHEN H , MARQUES-SILVA J . TG-pro: A SAT-based ATPG system [J ] . Journal on Satisfiability, Boolean Modeling and Computation , 2012 , 8 ( 1/2 ): 83 - 88 .

ROY S . Toward Zero Backtracks in Test Pattern Search Algorithms with Machine Learning [D ] . Auburn : Auburn University , 2021 .

SELSAM D , LAMM M , BÜNZ B , et al . Learning a SAT solver from single-bit supervision [EB/OL ] . ( 2019-03-12 )[ 2022-10-09 ] . https://doi.org/10.48550/arXiv.1802.03685 https://doi.org/10.48550/arXiv.1802.03685 .

SELSAM D , BJØRNER N . Guiding high-performance SAT solvers with unsat-core predictions [C ] // Lecture Notes in Computer Science . Cham : Springer International Publishing , 2019 : 336 - 353 .

KURIN V , GODIL S , WHITESON S , et al . Can Q -learning with graph networks learn a generalizable branching heuristic for a SAT solver? [EB/OL ] . ( 2019-09-26 )[ 2022-01-02 ] . https://arxiv.org/abs/1909.11830 https://arxiv.org/abs/1909.11830 .

MOSKEWICZ M W , MADIGAN C F , ZHAO Y , et al . Chaff: Engineering an efficient SAT solver [C ] // Proceedings of the 38th Annual Design Automation Conference . New York : ACM , 2001 : 530 - 535 .

RYAN L . Efficient Algorithms for Clause-Learning SAT Solvers [D ] . British Columbia : Simon Fraser University , 2002 .

ARJOVSKY M , CHINTALA S , BOTTOU L . Wasserstein generative adversarial networks [C ] // Proceedings of the 34th International Conference on Machine Learning - Volume 70 . New York : ACM , 2017 : 214 - 223 .

HOCHREITER S , SCHMIDHUBER J . Long short-term memory [J ] . Neural Computation , 1997 , 9 ( 8 ): 1735 - 1780 .

KIPF T N , WELLING M . Semi-supervised classification with graph convolutional networks [EB/OL ] . ( 2017-02-22 )[ 2022-10-09 ] . https://doi.org/10.48550/arXiv.1609.02907 https://doi.org/10.48550/arXiv.1609.02907 .

LIN T-Y , GOYAL P , GIRSHICK R , et al . Focal loss for dense object detection [C ] // Proceedings of the IEEE International Conference on Computer Vision . Venice : IEEE , 2017 : 2980 - 2988 .

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