A Reconfigurable Heterogeneous Memory Architecture and Memory Controller

JIN Xiao-zhong; LIU Hai-kun; LAI Hao; MAO Fu-bing; ZHANG Yu; LIAO Xiao-fei; JIN Hai

doi:10.12263/DZXB.20221257

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A Reconfigurable Heterogeneous Memory Architecture and Memory Controller

PAPERS | 更新时间：2025-12-08

- A Reconfigurable Heterogeneous Memory Architecture and Memory Controller
- ACTA ELECTRONICA SINICA Vol. 52, Issue 9, Pages: 3038-3051(2024)
- 作者机构：
  
  1.大数据技术与系统国家地方联合工程研究中心/服务计算与系统教育部重点实验室/集群与网格计算湖北省重点实验室，华中科技大学，湖北武汉 430074
  2.华中科技大学计算机科学与技术学院，湖北武汉 430074
- 作者简介：
- 基金信息：
  
  National Natural Science Foundation of China(62072198);Natural Science Foundation of Hubei Province(2021CFA037)
- DOI：10.12263/DZXB.20221257
  CLC： TP32
- Received：01 November 2022，
  
  Revised：2023-05-06，
  
  Published：25 September 2024
- 稿件说明：
移动端阅览
靳晓忠, 刘海坤, 赖皓, 等. 一种可重构异构内存架构和控制器[J]. 电子学报, 2024, 52(09): 3038-3051.

JIN Xiao-zhong, LIU Hai-kun, LAI Hao, et al. A Reconfigurable Heterogeneous Memory Architecture and Memory Controller[J]. Acta Electronica Sinica, 2024, 52(09): 3038-3051.
靳晓忠, 刘海坤, 赖皓, 等. 一种可重构异构内存架构和控制器[J]. 电子学报, 2024, 52(09): 3038-3051. DOI：10.12263/DZXB.20221257

JIN Xiao-zhong, LIU Hai-kun, LAI Hao, et al. A Reconfigurable Heterogeneous Memory Architecture and Memory Controller[J]. Acta Electronica Sinica, 2024, 52(09): 3038-3051. DOI：10.12263/DZXB.20221257

摘要

融合传统动态随机访问存储器（Dynamic Random Access Memory，DRAM）与新型非易失性内存（Non-Volatile Memory，NVM）可构建平行架构或层次架构的异构内存系统.平行架构的异构内存系统往往需要通过页迁移技术把热点数据从NVM迁移到DRAM以提高访存性能，然而在操作系统中实现热页监测和迁移会带来巨大的软件性能开销.硬件实现的层次架构由于增加了访存层次，对于访存局部性差的大数据应用反而增加了访存延迟.为此，本文提出可重构的异构内存架构，可以运行时在平行和层次架构间进行转换以动态适配不同应用的访存特性.设计了基于新型指令集架构RISC-V（Reduced Instruction Set Computing-V）的DRAM/NVM异构内存控制器，利用少量硬件计数器实现了访存踪迹统计和分析，并实现了DRAM和NVM物理页间的动态映射和高效迁移机制.实验表明，DRAM/NVM异构内存控制器可提高43%的应用性能.

Abstract

Heterogeneous memory systems composed of traditional dynamic random access memory (DRAM) and new non-volatile memory (NVM) can be organized in a horizontal architecture or a hierarchical architecture. The horizontal DRAM/NVM architecture often requires page migration technologies to improve memory access performance. However

hot page monitoring and migration implemented in operating systems would cause significant software performance overhead. The hardware-supported hierarchical architecture even increases the memory access latency for big data applications with poor data locality due to the deeper memory hierarchy. To this end

this paper proposes a reconfigurable heterogeneous memory architecture that can be converted between horizontal and hierarchical architectures at runtime to dynamically adapt the memory access characteristics of different applications. We design a DRAM/NVM heterogeneous memory controller (HMC) based on the new instruction set architecture RISC-V (Reduced Instruction Set Computing-V). The HMC uses a few hardware counters for memory access monitoring and analyzing

and achieves dynamic address mapping and eﬀicient page migration between DRAM and NVM pages. Experimental results show that the DRAM/NVM hybrid memory controller can improve application performance by 43%.

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references

MANDELMAN J A , DENNARD R H , BRONNER G B , et al . Challenges and future directions for the scaling of dynamic random-access memory (DRAM) [J ] . IBM Journal of Research and Development , 2002 , 46 ( 2/3 ): 187 - 212 .

BAHAR TALUKDER B M S , KERNS J , RAY B , et al . Exploiting DRAM latency variations for generating true random numbers [C ] // 2019 IEEE International Conference on Consumer Electronics (ICCE) . Piscataway : IEEE , 2019 : 1 - 6 .

RAMOS L E , GORBATOV E , BIANCHINI R . Page placement in hybrid memory systems [C ] // Proceedings of the International Conference on Supercomputing . New York : ACM , 2011 : 85 - 95 .

DHIMAN G , AYOUB R , ROSING T . PDRAM: A hybrid PRAM and DRAM main memory system [C ] // Proceedings of the 46th Annual Design Automation Conference . New York : ACM , 2009 : 664 - 669 .

MEZA J , CHANG J C , YOON H , et al . Enabling efficient and scalable hybrid memories using fine-granularity DRAM cache management [J ] . IEEE Computer Architecture Letters , 2012 , 11 ( 2 ): 61 - 64 .

QURESHI M K , SRINIVASAN V , RIVERS J A . Scalable high performance main memory system using phase-change memory technology [C ] // Proceedings of the 36th Annual International Symposium on Computer Architecture . New York : ACM , 2009 : 24 - 33 .

LIU H K , CHEN Y J , LIAO X F , et al . Hardware/software cooperative caching for hybrid DRAM/NVM memory architectures [C ] // Proceedings of the International Conference on Supercomputing . New York : ACM , 2017 : 1 - 10 .

王鹏 , 邹彬 , 刘金枝 , 等 . 基于Xilinx型FPGA系统单粒子效应评估方法研究 [J ] . 电子学报 , 2022 , 50 ( 11 ): 2716 - 2721 .

WANG P , ZOU B , LIU J Z , et al . Study on single event effect evaluation method based on Xilinx FPGA system [J ] . Acta Electronica Sinica , 2022 , 50 ( 11 ): 2716 - 2721 . (in Chinese)

田春生 , 陈雷 , 王源 , 等 . 面向FPGA的布局与布线技术研究综述 [J ] . 电子学报 , 2022 , 50 ( 5 ): 1243 - 1254 .

TIAN C S , CHEN L , WANG Y , et al . Review on technology of placement and routing for the FPGA [J ] . Acta Electronica Sinica , 2022 , 50 ( 5 ): 1243 - 1254 . (in Chinese)

王诲喆 , 唐丹 , 余子濠 , 等 . 开源芯片、RISC-V与敏捷开发 [J ] . 大数据 , 2019 , 5 ( 4 ): 50 - 66 .

WANG H Z , TANG D , YU Z H , et al . Open-source chip, RISC-V and agile development [J ] . Big Data Research , 2019 , 5 ( 4 ): 50 - 66 . (in Chinese)

MOHSENI Z , REVIRIEGO P . Reliability characterization and activity analysis of lowRISC internal modules against single event upsets using fault injection and RTL simulation [J ] . Microprocessors and Microsystems , 2019 , 71 : 102871 .

MATH S S , MANJULA R B , MANVI S S , et al . Data transactions on system-on-chip bus using AXI4 protocol [C ] // 2011 International Conference on Recent Advancements in Electrical, Electronics and Control Engineering . Piscataway : IEEE , 2011 : 423 - 427 .

YANG J , KIM J , HOSEINZADEH M , et al . An empirical guide to the behavior and use of scalable persistent memory [C ] // Proceedings of the 18th USENIX Conference on File and Storage Technologies . New York : ACM , 2020 : 169 - 182 .

LI P C , PRONOVOST C , WILSON W , et al . Beating OPT with statistical clairvoyance and variable size caching [C ] // Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems . New York : ACM , 2019 : 243 - 256 .

ILLANA J M . Design of an AXI-SDRAM interface IP in a RISC-V Processor [D ] . Barcelona : Universitat Politècnica de Catalunya , 2020 .

王孝远 , 廖小飞 , 刘海坤 , 等 . 面向大数据的异构内存系统 [J ] . 大数据 , 2018 , 4 ( 4 ): 15 - 34 .

WANG X Y , LIAO X F , LIU H K , et al . Big data oriented hybrid memory systems [J ] . Big Data Research , 2018 , 4 ( 4 ): 15 - 34 . (in Chinese)

LEE B C , IPEK E , MUTLU O , et al . Architecting phase change memory as a scalable dram alternative [C ] // Proceedings of the 36th annual international symposium on Computer architecture . New York : ACM , 2009 : 2 - 13 .

ALWADI M , KOMMAREDDY V R , HUGHES C , et al . Stealth-persist: Architectural support for persistent applications in hybrid memory systems [C ] // 2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA) . Piscataway : IEEE , 2021 : 139 - 152 .

RAYBUCK A , STAMLER T , ZHANG W , et al . HeMem: Scalable tiered memory management for big data applications and real NVM [C ] // Proceedings of the ACM SIGOPS 28th Symposium on Operating Systems Principles . New York : ACM , 2021 : 392 - 407 .

KIM J , CHOE W , AHN J . Exploring the design space of page management for multi-tiered memory systems [C ] // Proceedings of the 2021 USENIX Annual Technical Conference (ATC'21) . Virtual Event : USENIX , 2021 : 715 - 728 .

LIU H K , LIU R S , LIAO X F , et al . Object-level memory allocation and migration in hybrid memory systems [J ] . IEEE Transactions on Computers , 2020 , 69 ( 9 ): 1401 - 1413 .

MARUF A , GHOSH A , BHIMANI J , et al . MULTI-CLOCK: Dynamic tiering for hybrid memory systems [C ] // 2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA) . Piscataway : IEEE , 2022 : 925 - 937 .

裴颂文 , 姬燕飞 , 沈天马 , 等 . 基于双向哈希链表的异构内存页迁移机制 [J ] . 中国科学: 信息科学 , 2019 , 49 ( 9 ): 1138 - 1158 .

PEI S W , JI Y F , SHEN T M , et al . Migration mechanism of heterogeneous memory pages using a two-way Hash chain list [J ] . Scientia Sinica (Informationis) , 2019 , 49 ( 9 ): 1138 - 1158 . (in Chinese)

HAM T J , CHELEPALLI B K , XUE N , et al . Disintegrated control for energy-efficient and heterogeneous memory systems [C ] // Proceedings of the 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA) . New York : ACM , 2013 : 424 - 435 .

CHI Y , YUE J H , LIAO X F , et al . A hybrid memory architecture supporting fine-grained data migration [J ] . Frontiers of Computer Science , 2024 , 18 ( 2 ): 182103 .

DUAN Z H , LIU H K , LIAO X F , et al . HiNUMA: NUMA-aware data placement and migration in hybrid memory systems [C ] // 2019 IEEE 37th International Conference on Computer Design (ICCD) . Piscataway : IEEE , 2019 : 367 - 375 .

WU K , GUO Z H , HU G Z , et al . The storage hierarchy is not a hierarchy: optimizing caching on modern storage devices with orthus [C ] // Proceedings of the 19th USENIX Conference on File and Storage Technologies (FAST'21) . Virtual Event : USENIX , 2021 : 307 - 323 .

YI J F , DONG B C , DONG M K , et al . MT 2 : Memory bandwidth regulation on hybrid NVM/DRAM platforms [C ] // Proceedings of the 20th USENIX Conference on File and Storage Technologies (FAST'22) . Santa Clara : USENIX . 2022 : 199 - 216 .

ZHANG J , KWON M , GOUK D , et al . Revamping storage class memory with hardware automated memory-over-storage solution [C ] // Proceedings of the 48th Annual International Symposium on Computer Architecture . New York : ACM , 2021 : 762 - 775 .

LEIDEL J D . Stake: A coupled simulation environment for RISC-V memory experiments [C ] // Proceedings of the International Symposium on Memory Systems . New York : ACM , 2018 : 365 - 376 .

ZHANG J L , ZHA Y , BECKWITH N , et al . MEG: A RISCV-based system emulation infrastructure for near-data processing using FPGAs and high-bandwidth memory [J ] . ACM Transactions on Reconfigurable Technology and Systems , 2020 , 13 ( 4 ): 1 - 24 .

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