Pseudo Third-Order Delta-Sigma Modulator Applied to Internet of Things Sensors

WEI Cong; HUANG Li-jie; HU Wei; WEI Rong-shan

doi:10.12263/DZXB.20240155

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Pseudo Third-Order Delta-Sigma Modulator Applied to Internet of Things Sensors

PAPERS | 更新时间：2025-12-11

- Pseudo Third-Order Delta-Sigma Modulator Applied to Internet of Things Sensors
- ACTA ELECTRONICA SINICA Vol. 52, Issue 6, Pages: 2123-2130(2024)
- 作者机构：
  
  福州大学物理与信息工程学院，福建福州 350108
- 作者简介：
- 基金信息：
  
  National Natural Science Foundation of China(62274036)
- DOI：10.12263/DZXB.20240155
  CLC： TN432;
- Received：17 February 2024，
  
  Revised：2024-04-29，
  
  Published：25 June 2024
- 稿件说明：
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魏聪, 黄黎杰, 胡炜, 等. 一种应用于物联网传感器的伪三阶Delta-Sigma调制器[J]. 电子学报, 2024, 52(06): 2123-2130.

WEI Cong, HUANG Li-jie, HU Wei, et al. Pseudo Third-Order Delta-Sigma Modulator Applied to Internet of Things Sensors[J]. Acta Electronica Sinica, 2024, 52(06): 2123-2130.
魏聪, 黄黎杰, 胡炜, 等. 一种应用于物联网传感器的伪三阶Delta-Sigma调制器[J]. 电子学报, 2024, 52(06): 2123-2130. DOI：10.12263/DZXB.20240155

WEI Cong, HUANG Li-jie, HU Wei, et al. Pseudo Third-Order Delta-Sigma Modulator Applied to Internet of Things Sensors[J]. Acta Electronica Sinica, 2024, 52(06): 2123-2130. DOI：10.12263/DZXB.20240155

摘要

针对物联网传感器难以同时满足高分辨率与低功耗的瓶颈问题，本文设计了一种伪三阶离散时间delta-sigma调制器.该架构将一阶无源噪声整形SAR（Successive Approximation Register）量化器嵌入传统二阶delta-sigma调制器以实现更强的噪声整形能力.本文设计允许系统在更低的过采样率（Over Sampling Ratio，OSR）下获取更高的峰值SQNR（Signal-to-Quantizing Noise Ratio），有效缓解了系统精度和功耗之间的设计矛盾，并且减少了有源积分器的使用.针对传统有源加法器高功耗和无源加法器存在衰减不确定性的问题，本文提出了一种新型前馈求和量化电路，它具有对衰减不敏感的优势并且降低了第二级有源积分器的驱动压力，这进一步降低了系统的功耗.本文提出的delta-sigma调制器采用180 nm CMOS（Complementary Metal Oxide Semiconductor）工艺制造并测试.在电源电压1.4 V下，芯片测试功耗为47.2 μW.在带宽为8 kHz的测试条件下，调制器的DR（Dynamic Range）、峰值SNDR（Signal-to-Noise and Distortion Ratio）和SFDR（Spurious-Free Dynamic Range）分别为97.2 dB，96.6 dB和114.4 dB.因此，Schreier和Walden的SNDR FoM（Figure of Merit）优值达到了178.9 dB和0.053 pJ/step.本文提出的伪三阶delta-sigma调制器在功耗和分辨率之间实现了较好的权衡，为物联网领域的低功耗高分辨率调制器设计提供了较好的解决方案.

Abstract

This paper proposes a pseudo third-order discrete-time delta-sigma modulator to address the bottleneck of high resolution and low power consumption in Internet of Things (IoT) sensors. This architecture embeds a first-order passive noise-shaping SAR (Successive Approximation Register) quantizer into a conventional second-order delta-sigma modulator to achieve stronger noise-shaping capabilities. This allows the system to achieve higher peak SQNR (Signal-to-Quantizing Noise Ratio) at lower OSR (Over Sampling Ratio)

effectively mitigating the design trade-off between system accuracy and power consumption

while reducing the use of active integrators. In response to the high power consumption of traditional active adders and the attenuation uncertainty of passive adders

this paper proposes a novel feedforward sum quantization circuit. It has the advantage of being insensitive to attenuation and reduces the driving pressure of the second stage active integrator

which further reduces the power consumption of the system. The proposed delta-sigma modulator is manufactured and tested using a 180 nm CMOS (Complementary Metal Oxide Semiconductor) process. At a power supply voltage of 1.4 V

the tested power consumption of the chip is 47.2 μW. With a bandwidth of 8 kHz

the DR (Dynamic Range)

peak SNDR (Signal-to-Noise and Distortion Ratio)

and SFDR (Spurious-Free Dynamic Range) of the modulator are 97.2 dB

96.6 dB

and 114.4 dB

respectively. Therefore

figure-of-merit (FoM) Schreier and Walden for SNDR are 178.9 dB and 0.053 pJ/step. The pseudo third-order delta-sigma modulator proposed in this article achieves a good balance between power consumption and resolution

providing a good solution for low-power and high-resolution modulator design in the field of the IoTs.

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references

张畅 , 佟星元 . 工艺-电压-温度综合稳健的亚1 V 10位SAR ADC [J ] . 电子学报 , 2023 , 51 ( 8 ): 2050 - 2057 .

ZHANG C , TONG X Y . A Sub-1 V 10 bit SAR ADC robust against process-voltage-temperature variation [J ] . Acta Electronica Sinica , 2023 , 51 ( 8 ): 2050 - 2057 . (in Chinese)

SHEN Y T , LI H Y , BINDRA H S , et al . A 14-bit oversampled SAR ADC with mismatch error shaping and analog range compensation [J ] . IEEE Transactions on Circuits and Systems II: Express Briefs , 2023 , 70 ( 5 ): 1719 - 1723 .

LIU J X , HSU C K , TANG X Y , et al . Error-feedback mismatch error shaping for high-resolution data converters [J ] . IEEE Transactions on Circuits and Systems I: Regular Papers , 2019 , 66 ( 4 ): 1342 - 1354 .

GUO W J , SUN N . A 12b-ENOB 61 <math id="M32"><mi mathvariant="normal">μ</mi><mi mathvariant="normal">W</mi></math> https://html.publish.founderss.cn/rc-pub/api/common/picture?pictureId=64211234&type= 2.96333337 https://html.publish.founderss.cn/rc-pub/api/common/picture?pictureId=64211229&type= 4.74133301 noise-shaping SAR ADC with a passive integrator [C ] // ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference . Piscataway : IEEE , 2016 : 405 - 408 .

ZHUANG H Y , GUO W J , LIU J X , et al . A second-order noise-shaping SAR ADC with passive integrator and tri-level voting [J ] . IEEE Journal of Solid-State Circuits , 2019 , 54 ( 6 ): 1636 - 1647 .

LIU J X , WANG X , GAO Z J , et al . A 90-dB-SNDR calibration-free fully passive noise-shaping SAR ADC with 4 × passive gain and second-order DAC mismatch error shaping [J ] . IEEE Journal of Solid-State Circuits , 2021 , 56 ( 11 ): 3412 - 3423 .

郭仲杰 , 许睿明 , 程新齐 , 等 . 面向亿级CMOS图像传感器的高速全并行两步式ADC设计方法 [J ] . 电子学报 , 2023 , 51 ( 8 ): 2067 - 2075 .

GUO Z J , XU R M , CHEN X Q , et al . High speed fully parallel two-step ADC design method for hundred million level CMOS image sensors [J ] . Acta Electronica Sinica , 2023 , 51 ( 8 ): 2067 - 2075 . (in Chinese)

WANG L , LIU S B , ZHANG Y B , et al . A 44-μW, 91.3-dB SNDR DT Δ Σ modulator with second-order noise-shaping SAR quantizer [J ] . IEEE Transactions on Circuits and Systems I: Regular Papers , 2023 , 70 ( 9 ): 3575 - 3583 .

GUO Y K , JIN J , LIU X M , et al . A 372 μW 10 kHz-BW 109.2 dB-SNDR nested delta-sigma modulator using hysteresis-comparison MSB-pass quantization [J ] . IEEE Journal of Solid-State Circuits , 2023 , 58 ( 9 ): 2554 - 2563 .

HAN J H , CHO K I , KIM H J , et al . A 96dB dynamic range 2kHz bandwidth 2nd order delta-sigma modulator using modified feed-forward architecture with delayed feedback [J ] . IEEE Transactions on Circuits and Systems II: Express Briefs , 2021 , 68 ( 5 ): 1645 - 1649 .

WEI C , WEI R S , HUANG L J , et al . A 1.2 V 2.3 <math id="M33"><mi mathvariant="normal">μ</mi></math> https://html.publish.founderss.cn/rc-pub/api/common/picture?pictureId=64211230&type= 2.96333337 https://html.publish.founderss.cn/rc-pub/api/common/picture?pictureId=64211248&type= 1.69333339 W 94.7 dB DR delta-sigma modulator with dynamic-range enhancement and tri-level CDAC [C ] // 2023 IEEE Asian Solid-State Circuits Conference (A-SSCC) . Piscataway : IEEE , 2023 : 1 - 3 .

HU Y P , ZHAO Y B , QU W Y , et al . A 2.87μW 1kHz-BW 94.0dB-SNDR 2-0 MASH ADC using FIA with dynamic-body-biasing assisted CLS technique [C ] // 2022 IEEE International Solid-State Circuits Conference (ISSCC) . Piscataway : IEEE , 2022 : 410 - 412 .

SCHREIER R , SILVA J , STEENSGAARD J , et al . Design-oriented estimation of thermal noise in switched-capacitor circuits [J ] . IEEE Transactions on Circuits and Systems I: Regular Papers , 2005 , 52 ( 11 ): 2358 - 2368 .

ASHWIN KUMAR R S , KRISHNAPURA N , BANERJEE P . Analysis and design of a discrete-time delta-sigma modulator using a cascoded floating-inverter-based dynamic amplifier [J ] . IEEE Journal of Solid-State Circuits , 2022 , 57 ( 11 ): 3384 - 3395 .

ZHAO Y B , ZHAO M L , TAN Z C . Fully dynamic zoom-ADC based on improved swing-enhanced FIAs using CLS technique with 1250 × bandwidth/power scalability‍ [J ] . IEEE Transactions on Circuits and Systems II: Express Briefs , 2023 , 70 ( 6 ): 1901 - 1905 .

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