High-Speed Column Bus Readout Method Based on Negative Capacitance Circuit

XU Rui-ming; GUO Zhong-jie; LIU Sui-yang; YU Ning-mei

doi:10.12263/DZXB.20240948

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High-Speed Column Bus Readout Method Based on Negative Capacitance Circuit

PAPERS | 更新时间：2025-07-24

- High-Speed Column Bus Readout Method Based on Negative Capacitance Circuit
- ACTA ELECTRONICA SINICA Vol. 53, Issue 4, Pages: 1192-1200(2025)
- 作者机构：
  
  西安理工大学自动化与信息工程学院，陕西西安 710048
- 作者简介：
- 基金信息：
  
  National Natural Science Foundation of China(62171367)
- DOI：10.12263/DZXB.20240948
  CLC： TN47;
- Received：17 October 2024，
  
  Revised：2025-04-17，
  
  Published：25 April 2025
- 稿件说明：
移动端阅览
许睿明, 郭仲杰, 刘绥阳, 等. 基于负电容电路的高速列总线读出方法[J]. 电子学报, 2025, 53(04): 1192-1200.

XU Rui-ming, GUO Zhong-jie, LIU Sui-yang, et al. High-Speed Column Bus Readout Method Based on Negative Capacitance Circuit[J]. Acta Electronica Sinica, 2025, 53(04): 1192-1200.
许睿明, 郭仲杰, 刘绥阳, 等. 基于负电容电路的高速列总线读出方法[J]. 电子学报, 2025, 53(04): 1192-1200. DOI：10.12263/DZXB.20240948

XU Rui-ming, GUO Zhong-jie, LIU Sui-yang, et al. High-Speed Column Bus Readout Method Based on Negative Capacitance Circuit[J]. Acta Electronica Sinica, 2025, 53(04): 1192-1200. DOI：10.12263/DZXB.20240948

摘要

针对超大面阵CMOS图像传感器列总线建立时间过长的问题，本文提出了一种高速列总线信号读出方法.该方法基于负电容技术，将负电容电路集成到列级读出电路中，抵消列总线寄生电容对列总线信号建立时间的负面影响.同时，基于动态环路稳定性调节技术，平衡了读出速度与环路稳定性的设计矛盾.本文基于55 nm 1P4M CMOS工艺对提出的高速列总线读出方法完成了详细电路设计和全面仿真验证.在像素尺寸10 μm × 10 μm，尾电流为5 μA，列总线输出电压摆幅为1.2 V的设计条件下，列总线信号上升建立时间从1.721 μs减少至1.204 μs，降低了30.04%.列总线信号下降建立时间从5.780 μs降低至2.816 μs，降低了51.28%.此外，行固定模式噪声从1.30%降低到0.01%.在1.6 W的功耗下，本文设计的大面阵CMOS图像传感器的帧率和动态范围分别达到了27帧每秒和85 dB，为大面阵高速低功耗CMOS图像传感器的设计提供了一定的理论支撑.

Abstract

Aiming at the problem of the long establishment time of the column bus signal in large array CMOS image sensors

a high-speed column bus signal reading method is proposed in this paper. Based on negative capacitance technology

the negative capacitance circuit is integrated into the column-level readout circuit to offset the negative influence of column bus parasitic capacitance on the establishment time of column bus signal. At the same time

based on the dynamic loop stability regulation technology

the design contradiction between readout speed and loop stability is balanced. Based on 55 nm 1P4M CMOS technology

detailed circuit design and comprehensive simulation verification of the proposed high-speed column bus readout method are completed in this paper. Under the design conditions that the pixel size is 10 μm × 10 μm

the tail current is 5 μA

and the column bus output voltage swing is 1.2 V

the rise time of the column bus signal is reduced from 1.721 μs to 1.204 μs

which is reduced by 30.04%. The fall time of column bus signal is reduced by 51.28% from 5.780 μs to 2.816 μs. In addition

row fixed mode noise (RFPN) is reduced from 1.30% to 0.01%. Under the power consumption of 1.6 W

the frame rate and dynamic range of the large array CMOS image sensor designed in this paper reach 27 fps and 85 dB respectively. It provides a certain theoretical support for the design of large array high-speed and low-power CMOS image sensors.

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references

XU R M , GUO Z J , YU N M , et al . A high-speed 13-bit two-step single-slope ADC for large array CMOS image sensors [J ] . Integration , 2023 , 91 : 119 - 125 .

GEORGE S S , BOCKO M F , IGNJATOVIC Z . Current sensing-assisted active pixel sensor for high-speed CMOS image sensors [J ] . IEEE Sensors Journal , 2015 , 15 ( 8 ): 4365 - 4372 .

GAO J , ZHANG D Z , NIE K M , et al . Analysis and Optimization design of the column bus parasitic effects on large-array CMOS image sensor [J ] . Microelectronics Journal , 2020 , 96 : 104681 .

XU J T , LI W , NIE K M , et al . A method to reduce the effect on image quality caused by resistance of column bus [J ] . IEEE Transactions on Very Large Scale Integration (VLSI) Systems , 2019 , 27 ( 1 ): 173 - 181 .

GUO Z J , CHENG X Q , XU R M , et al . A 1Gpixel 10FPS CMOS image sensor using pixel array high-speed readout technology [J ] . Integration , 2023 , 89 : 114 - 122 .

FUNATSU R , HUANG S , YAMASHITA T , et al . 6.2 133Mpixel 60fps CMOS image sensor with 32-column shared high-speed column-parallel SAR ADCs [C ] // 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of Technical Papers . Piscataway : IEEE , 2015 : 1 - 3 .

KIM M S , KANG D U , LEE D H , et al . Study on the fast signal transfer for large-area X-ray image sensors [C ] // 2013 IEEE Nuclear Science Symposium and Medical Imaging Conference (2013 NSS/MIC) . Piscataway : IEEE , 2013 : 1 - 5 .

KIM M S , KANG D U , LEE D H , et al . Fast signal transfer in a large-area X-ray CMOS image sensor [J ] . Journal of Instrumentation , 2014 , 9 ( 8 ): P08011 .

LE-THAI H , XHAKONI A , GIELEN G . A column-and-row-parallel CMOS image sensor with thermal and 1/f noise suppression techniques [C ] // ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference . Piscataway : IEEE , 2016 : 221 - 224 .

GUO Z J , YU N M , WU L S . A synchronous driving approach based on adaptive delay phase-locked loop for stitching CMOS image sensor [J ] . IEICE Electronics Express , 2020 , 17 ( 3 ): 20190642 .

BOGAERTS J , LAFAILLE R , BORREMANS M , et al . 6.3 105×65mm2 391Mpixel CMOS image sensor with >78dB dynamic range for airborne mapping applications [C ] // 2016 IEEE International Solid-State Circuits Conference (ISSCC) . Piscataway : IEEE , 2016 : 114 - 115 .

AGARWAL A , HANSRANI J , BAGWELL S , et al . A 316MP, 120FPS, high dynamic range CMOS image sensor for next generation immersive displays [J ] . Sensors , 2023 , 23 ( 20 ): 23208383 .

LEVSKI D , WÄNY M , CHOUBEY B . A 1- $\mu$ s ramp time 12-bit column-parallel flash TDC-interpolated single-slope ADC with digital delay-element calibration [J ] . IEEE Transactions on Circuits and Systems I: Regular Papers , 2019 , 66 ( 1 ): 54 - 67 .

郭仲杰 , 苏昌勖 , 许睿明 , 等 . 基于粗细量化并行与TDC混合的CMOS图像传感器列级ADC设计方法 [J ] . 电子学报 , 2024 , 52 ( 2 ): 486 - 499 .

GUO Z J , SU C X , XU R M , et al . Column level ADC design method of CMOS image sensor based on coarse and fine quantization parallel and TDC hybrid [J ] . Acta Electronica Sinica , 2024 , 52 ( 2 ): 486 - 499 . (in Chinese)

郭仲杰 , 王杨乐 , 许睿明 , 等 . 应用于CMOS图像传感器的高速全差分两步式ADC设计方法 [J ] . 电子与信息学报 , 2023 , 45 ( 9 ): 3410 - 3419 .

GUO Z J , WANG Y L , XU R M , et al . High-speed fully differential two-step ADC design method for CMOS image sensor [J ] . Journal of Electronics & Information Technology , 2023 , 45 ( 9 ): 3410 - 3419 . (in Chinese)

郭仲杰 , 程新齐 , 余宁梅 , 等 . 面向超大面阵CMOS图像传感器的列总线自加速建立方法研究 [J ] . 电子学报 , 2023 , 51 ( 6 ): 1581 - 1589 .

GUO Z J , CHENG X Q , YU N M , et al . Research on self-accelerated establishment method of column bus for super large array CMOS image sensor [J ] . Acta Electronica Sinica , 2023 , 51 ( 6 ): 1581 - 1589 . (in Chinese)

郭仲杰 , 许睿明 , 程新齐 , 等 . 面向亿级CMOS图像传感器的高速全并行两步式ADC设计方法 [J ] . 电子学报 , 2023 , 51 ( 8 ): 2067 - 2075 .

GUO Z J , XU R M , CHENG X Q , et al . High speed fully parallel two-step ADC design method for hundred million level CMOS image sensors [J ] . Acta Electronica Sinica , 2023 , 51 ( 8 ): 2067 - 2075 . (in Chinese)

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School of Automation and Engineering, Xi'an University of Technology

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