Composite Current Source Stage Delay Calculation Method Based on Dynamic Capacitance

GUO Jing-jing; ZHA Pei-wen; ZHANG Shu-gang; CAI Zhi-kuang

doi:10.12263/DZXB.20241149

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Composite Current Source Stage Delay Calculation Method Based on Dynamic Capacitance

PAPERS | 更新时间：2025-12-10

- Composite Current Source Stage Delay Calculation Method Based on Dynamic Capacitance
- ACTA ELECTRONICA SINICA Vol. 53, Issue 7, Pages: 2428-2440(2025)
- 作者机构：
  
  南京邮电大学集成电路科学与工程学院（产教融合学院），江苏南京 210023
- 作者简介：
- 基金信息：
  
  Natural Science Foundation of Jiangsu Province(BK20240637)
- DOI：10.12263/DZXB.20241149
  CLC： TN47;TN401
- Received：20 December 2024，
  
  Revised：2025-06-24，
  
  Published：25 July 2025
- 稿件说明：
移动端阅览
郭静静, 查佩文, 张树钢, 等. 基于动态电容的复合电流源阶段延时计算方法[J]. 电子学报, 2025, 53(07): 2428-2440.

GUO Jing-jing, ZHA Pei-wen, ZHANG Shu-gang, et al. Composite Current Source Stage Delay Calculation Method Based on Dynamic Capacitance[J]. Acta Electronica Sinica, 2025, 53(07): 2428-2440.
郭静静, 查佩文, 张树钢, 等. 基于动态电容的复合电流源阶段延时计算方法[J]. 电子学报, 2025, 53(07): 2428-2440. DOI：10.12263/DZXB.20241149

GUO Jing-jing, ZHA Pei-wen, ZHANG Shu-gang, et al. Composite Current Source Stage Delay Calculation Method Based on Dynamic Capacitance[J]. Acta Electronica Sinica, 2025, 53(07): 2428-2440. DOI：10.12263/DZXB.20241149

摘要

深亚微米工艺下传统时序模型的延时计算不再准确，针对米勒效应愈发不可忽视、互连线电阻性增大和互连线延时比重越来越大等问题，本文提出一种基于动态电容的复合电流源阶段延时计算方法.首先，本文引入基于电压的插值方法支持复合电流源的延时计算；其次，构建Π模型为负载的单元延时计算方法，采用多阈值分析改进有效电容并推导动态电容，实现迭代计算流程；随后，扩展动态电容概念到阶段延时计算中，实现以分布式RC网络作为负载的阶段延时计算方法，并使用机器学习优化互连线延时.基于ASAP 7 nm Predictive PDK （ASAP 7）工艺，本文提出的阶段延时计算方法与SPICE（Simulation Program with Integrated Circuit Emphasis）对比分别实现了1.49%、3.16%、1.70%、0.88%的单元延时、单元转换时间、互连线延时与互连线转换时间的平均相对误差，平均在4~5次迭代后达到收敛.

Abstract

With the deep sub-micron technology in integrated circuit develops

Miller effect becomes non-negligible and the increasing interconnection resistivity increases

leading to increased delay time prediction inaccuracy. A composite current source stage delay calculation method based on dynamic capacitance is proposed in this paper. A voltage-based interpolation method is firstly introduced to support the delay calculation of composite current source. A cell delay calculation method with a Π model load is then established and a multi-threshold analysis is used to improves the effective capacitance

derives the dynamic capacitance and realizes the iterative calculation process. The dynamic capacitance concept is applied to the stage delay calculation

and used to realize the stage delay calculation method with distributed RC network as the load. By using machine learning

the interconnect wire delay is further optimized. Based on the ASAP 7 nm predictive PDK (ASAP 7) technology

the stage delay calculation method proposed in this paper achieves an average relative error of 1.49%

3.16%

1.70%

and 0.88% for the cell delay

cell transition time

interconnect line delay

and interconnect line transition time

respectively

compared with simulation program with integrated circuit emphasis (SPICE) simulation

the stage delay calculation method reaches convergence with about 4~5 iterations.

关键词

Keywords

references

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