BottleneckNet: A Graph Neural Network for Post-Synthesis Timing Bottleneck Prediction in Large-Scale Digital ICs

HE Guang-peng; DI Zhi-xiong; DENG Yu-jiao; CHEN Xuan; ZHANG Ze-tao; LIU Yang

doi:10.12263/DZXB.20250798

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BottleneckNet: A Graph Neural Network for Post-Synthesis Timing Bottleneck Prediction in Large-Scale Digital ICs

PAPERS | 更新时间：2026-04-24

- BottleneckNet: A Graph Neural Network for Post-Synthesis Timing Bottleneck Prediction in Large-Scale Digital ICs
- ACTA ELECTRONICA SINICA Vol. 53, Issue 12, Pages: 4518-4526(2025)
- 作者机构：
  
  1.西南交通大学信息科学与技术学院，四川成都 611730
  2.西南交通大学集成电路学院，四川成都 611730
  3.西安电子科技大学集成电路学部，陕西西安 710126
  4.华为技术有限公司海思半导体业务部，广东深圳 518129
- 作者简介：
- 基金信息：
  
  National Natural Science Foundation of China(62374138)
- DOI：10.12263/DZXB.20250798
  CLC： TN402;
- Received：12 September 2025，
  
  Accepted：22 December 2025，
  
  Published：25 December 2025
- 稿件说明：
移动端阅览
何广鹏, 邸志雄, 邓雨姣, 等. BottleneckNet:一种面向大规模数字芯片的逻辑综合后阶段时序瓶颈预测的GNN模型[J]. 电子学报, 2025, 53(12): 4518-4526.

HE Guang-peng, DI Zhi-xiong, DENG Yu-jiao, et al. BottleneckNet: A Graph Neural Network for Post-Synthesis Timing Bottleneck Prediction in Large-Scale Digital ICs[J]. Acta Electronica Sinica, 2025, 53(12): 4518-4526.
何广鹏, 邸志雄, 邓雨姣, 等. BottleneckNet:一种面向大规模数字芯片的逻辑综合后阶段时序瓶颈预测的GNN模型[J]. 电子学报, 2025, 53(12): 4518-4526. DOI：10.12263/DZXB.20250798

HE Guang-peng, DI Zhi-xiong, DENG Yu-jiao, et al. BottleneckNet: A Graph Neural Network for Post-Synthesis Timing Bottleneck Prediction in Large-Scale Digital ICs[J]. Acta Electronica Sinica, 2025, 53(12): 4518-4526. DOI：10.12263/DZXB.20250798

摘要

在超大规模数字芯片（Very Large Scale Integration，VLSI）设计流程中，逻辑综合阶段是连接架构设计与物理实现的桥梁.然而，逻辑综合工具分析得出的初始时序瓶颈路径与布局布线（Placement and Routing，P

R）完成后的真实时序瓶颈之间往往存在显著差异.这种“时序不一致性”主要源于两个维度：首先，在综合阶段，由于物理布局信息缺失，电子设计自动化（Electronic Design Automation，EDA）工具通常采用线网负载模型估算互连线时延，难以捕捉深亚微米工艺下复杂的寄生参数效应；其次，现代芯片内部逻辑门种类繁多且拓扑连接高度复杂，这显著增加了在逻辑综合阶段进行准确静态时序分析（Static Timing Analysis，STA）的计算难度.为了解决上述挑战，本文提出一种面向大规模数字芯片的时序瓶颈预测模型——BottleneckNet.首先，在特征工程方面，针对大规模设计网表规模过大导致深度学习模型难以训练的问题，本文提出了一种基于寄存器子图（Register Sub-Graph，RSG）概念的网表特征提取方法.该方法通过对网表拓扑进行结构化剪枝，仅保留寄存器间的关键组合逻辑信息.该特征提取流程可以在

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的时间复杂度下完成，从而满足了工业级大规模网表的处理需求.在模型架构方面，本文设计了一种基于图神经网络（Graph Neural Network，GNN）的双通道特征传播模型，该模型能够同时捕捉电路的全局特征与局部逻辑网络拓扑信息.通过融合双通道特征，BottleneckNet能够实现对布局布线后时序瓶颈的精准感知.本文基于多组开源大规模设计构建了完备的测试数据集，实验结果表明，本文提出的BottleneckNet模型展现出优异的综合性能.在处理效率方面，该方法能够在分钟级时间内完成百万门级设计的特征提取与推理任务.在预测精度方面，针对时序最差的5%~20%时序瓶颈路径，本文方法的预测准确率不仅显著优于轻量级梯度提升机（Light Gradient Boosting Machine，LightGBM）模型，且远高于工业界主流逻辑综合工具Synopsys公司的Design Compiler（DC）在综合阶段给出的计算结果.该研究成果对于指导逻辑综合阶段后的时序优化、缩短芯片研发迭代周期具有重要的理论意义与工程应用价值.

Abstract

In the design flow of very large scale integration (VLSI)

the logic synthesis stage serves as a bridge between architectural design and physical implementation. However

there is often a significant discrepancy between the initial timing bottleneck paths analyzed by logic synthesis tools and the actual timing bottlenecks after placement and routing (P

R). This “timing inconsistency” mainly originates from two dimensions: first

in the synthesis stage

due to the lack of physical layout information

electronic design automation (EDA) tools usually employ wire load models to estimate interconnect delays

which makes it difficult to capture complex parasitic effects under deep sub-micron processes; second

modern chips contain a wide variety of logic gates and highly complex topological connections

which significantly increases the computational difficulty of accurate static timing analysis (STA) during logic synthesis. To address these

challenges

this paper proposes BottleneckNet

a timing bottleneck prediction model for large-scale digital chips. First

in terms of feature engineering

to address the issue where large-scale design netlists are too large for deep learning models to train

a netlist feature extraction method based on the concept of register sub-graph (RSG) is proposed. This method performs structural pruning on the netlist topology

retaining only the critical combinational logic information between registers. This feature extraction process can be completed with a time complexity of

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6.94266701

3.21733332

thereby meeting the processing requirements for industrial large-scale netlists. In terms of model architecture

a dual-channel feature propagation model based on graph neural network (GNN) is designed. This model can simultaneously capture global features and local logic network topological information of the circuit. By fusing dual-channel features

BottleneckNet achieves accurate perception of post-P

R timing bottlenecks. A complete test dataset was constructed based on multiple sets of open-source large-scale designs. Simulation experiment results show that the proposed BottleneckNet model demonstrates excellent comprehensive performance. In terms of processing efficiency

the method can complete feature extraction and inference tasks for million-gate level designs within minutes. In terms of prediction accuracy

for the worst 5%~20% timing bottleneck paths

the

prediction accuracy of the proposed method is not only significantly better than the light gradient boosting machine (LightGBM) model

but also much higher than the calculation results given by Synopsys design compiler (DC)

a mainstream industrial logic synthesis tool

during the synthesis stage. The research results have important theoretical significance and engineering application value for guiding timing optimization after the logic synthesis stage and shortening the chip R

D cycle.

关键词

Keywords

references

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