Test schemes with multiple scan chains can speed up test schedule and are more fitting for testing VLSI

and hence a test data compression scheme is proposed and applied to multiple scan chain testing.Treatment model of cyclic shift introduced can dynamically adjust reference vectors

retain don't care bits in vectors and increase extensions of test vectors

and thus compatibility and inverse compatibility between vectors can be heightened.At the same time

an efficient technique for replacement of reference vectors can be exploited to further heighten correlations between vectors and decrease number of code words.Moreover

existing shift registers can be utilized to lower unnecessary hardware overhead.The experiment results demonstrate that the proposed scheme can further improve test compression ratios

meet deterministic fault test and hybrid built-in self test under maintaining advantages of multiple scan chain testing.