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A VLSI Architecture Evaluation of a Syntax Element Level Parallel Arithmetic Entropy Coder for Parallel H.264 Encoder
更新时间:2025-07-16
    • A VLSI Architecture Evaluation of a Syntax Element Level Parallel Arithmetic Entropy Coder for Parallel H.264 Encoder

    • Acta Electronica Sinica   Vol. 40, Issue 2, Pages: 400-405(2012)
    • DOI:10.3969/j.issn.0372-2112.2012.02.031    

      CLC: TP332.2
    • Published:2012

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  • CHEN Sheng-gang, CHEN Shu-ming, GU Hui-tao, et al. A VLSI Architecture Evaluation of a Syntax Element Level Parallel Arithmetic Entropy Coder for Parallel H.264 Encoder[J]. Acta Electronica Sinica, 2012, 40(2): 400-405. DOI: 10.3969/j.issn.0372-2112.2012.02.031.

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