In this paper

based on the smart home system as one of the most typical applications of wireless multimedia sensor networks

we abstract the system model.In order to provide multimedia data in the network to the user quickly and easily

we design a gateway in smart home system to support the interconnection with heterogeneous networks.We use HDLC (High Data Link Control) protocol to guarantee reliable data transmission in the design of the gateway access to the PSTN

and implement the HDLC protocol based on FPGA.In order to improve the processing efficiency of HDLC chip

receiving buffer is designed as a multi-Block FIFO and supports to read and write multiple Blocks concurrently.The multi-Block receiving buffer includes the independent BRAM mode and shared BRAM mode to adapt to a variety of requirements and reduce the CPU interrupt effectively.Modelsim is utilized to simulate the function of FPGA-based HDLC chip to verify reading and writing

transmitting and receiving

time slot

interrupts and other functions.Finally

verilog code runs in the actual test board and the FPGA-based HDLC chip is verified on the test board.