BIST Scheme of Parallel Folding Counters

LIANG Hua-guo; LI Xin; CHEN Tian; WANG Wei; YI Mao-xiang

doi:10.3969/j.issn.0372-2112.2012.05.027

您当前的位置：

首页 >

文章列表页 >

BIST Scheme of Parallel Folding Counters

更新时间：2025-07-16

- BIST Scheme of Parallel Folding Counters
- Acta Electronica Sinica Vol. 40, Issue 5, Pages: 1030-1033(2012)
- 作者机构：
  
  1. 合肥工业大学电子科学与应用物理学院,安徽,合肥,23009
  2. 合肥工业大学计算机与信息学院,安徽,合肥,23009
  3. 合肥工业大学电子科学与应用物理学院,安徽,合肥,23009
  4. 合肥工业大学计算机与信息学院,安徽,合肥,23009
- 作者简介：
- 基金信息：
- DOI：10.3969/j.issn.0372-2112.2012.05.027
  CLC： 306.2
- Published：2012
- 稿件说明：
移动端阅览
LIANG Hua-guo, LI Xin, CHEN Tian, et al. BIST Scheme of Parallel Folding Counters[J]. Acta Electronica Sinica, 2012, 40(5): 1030-1033.
DOI：

LIANG Hua-guo, LI Xin, CHEN Tian, et al. BIST Scheme of Parallel Folding Counters[J]. Acta Electronica Sinica, 2012, 40(5): 1030-1033. DOI： 10.3969/j.issn.0372-2112.2012.05.027.

摘要

本文提出了一种新的基于初始状态的并行折叠计数结构

并给出了建议的多扫描链的BIST方案.与国际上同类方法相比

该方案需要更少的测试数据存储容量、更短的测试应用时间

其平均测试应用时间是同类方案的0.265%

并且能很好地适用于传统的EDA设计流程.

Abstract

A new architecture of parallel folding counters is presented and a preferred BIST scheme of multiple scan chains is advised.Compared to international similar approaches

the proposed scheme needs less storage volume and shorter test application time

test application time is only as much as 0.265% of other similar scheme

and is compatible with traditional scan-based design flow.

关键词

Keywords

references

Views

下载量

CSCD

Alert me when the article has been cited

提交

Tools

Publicity Resources

Low Power Test Data Compression Technique Based on Reconfigurable MUXs Network

A Test Data Compression Scheme Based on Mixed Fixed and Variable Run-length Coding in Virtual Block

The Algorithm of Filling X Bits in Dual-Run-Length Coding

A Hybrid Run-Length Coding for Soc Test Data Compression

Related Author

LI Xiao-wei

HAN Yin-he

WU Xi

LIU Jun

HUANG Zheng-feng

SHI Feng

LIANG Hua-guo

ZHAN Wen-fa

Related Institution

Graduate University of Chinese Academy of SciencesBeijing 100490China

Key Laboratory of Computer System and ArchitectureInstitute of Computing TechnologyChinese Academy of SciencesBeijing 100190China

School of Computer and InformationHefei University of TechnologyHefeiAnhui 230009China

Graduate University of Chinese Academy of Sciences

Key Laboratory of Computer System and Architecture,Institute of Computing Technology,Chinese Academy of Sciences

⁰