Inter-Thread Interference Analysis for Real-Time WCET Estimations of Multi-Core Architectures

doi:10.3969/j.issn.0372-2112.2012.07.015

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Inter-Thread Interference Analysis for Real-Time WCET Estimations of Multi-Core Architectures

更新时间：2025-07-08

- Inter-Thread Interference Analysis for Real-Time WCET Estimations of Multi-Core Architectures
- Acta Electronica Sinica Vol. 40, Issue 7, Pages: 1372-1378(2012)
- 作者机构：
  
  1. 国防科学技术大学计算机学院,湖南,长沙,410073
  2. 国防科学技术大学并行与分布处理国家重点实验室,湖南,长沙,410073
  3. 国防科学技术大学计算机学院,湖南,长沙,410073
  4. 国防科学技术大学并行与分布处理国家重点实验室,湖南,长沙,410073
- 作者简介：
- 基金信息：
  
  Ph.D. Programs Foundation of Ministry of Education of China (No.20104307110005);Outstanding Postgraduate Student Innovation Fund of National University of Defense Technology (No.B100601);Funded by Postgraguate Technology Innovation Program of Hunan Province (No.CX2010B026)
- DOI：10.3969/j.issn.0372-2112.2012.07.015
  CLC： TP316
- Published：2012
- 稿件说明：
移动端阅览
Inter-Thread Interference Analysis for Real-Time WCET Estimations of Multi-Core Architectures[J]. Acta Electronica Sinica, 2012, 40(7): 1372-1378.
DOI：

Inter-Thread Interference Analysis for Real-Time WCET Estimations of Multi-Core Architectures[J]. Acta Electronica Sinica, 2012, 40(7): 1372-1378. DOI： 10.3969/j.issn.0372-2112.2012.07.015.

摘要

在共享Cache的多核处理器中

线程在共享Cache中的指令可能被其他并行线程的指令替换

从而导致了线程间在共享Cache上的干扰.多核结构下WCET估值需要考虑并行线程间在共享Cache上的干扰.针对当前典型的共享Cache和共享总线的多核结构

本文提出了一种迭代的WCET估值分析方法.考虑共享总线对共享Cache访问的时序影响

基于该时序分析线程间在共享Cache上的干扰

得到较精确的WCET估值.理论分析证明了该方法的有效性

实验结果表明本文的分析方法较之当前的两种方法分别可以提高21%和14%的精确度.

Abstract

In a shared-cache multi-core architecture one thread may interfere with a second thread if the second one tries to access the shared cache simultaneously.Consequently

this causes the eviction of the second thread instructions.To track this challenge

designers need to consider runtime inter-thread interference while analyzing WCET of a real-time application on multi-core architectures.This paper proposes an iterative approach for WCET estimation which considers the circular dependence between shared bus and the runtime inter-thread interference in shared cache.Our approach analyzes inter-thread interference in shared cache based on access timings

which combines static analysis and dynamic timing estimation.The iterative method presented can improve the tightness of WCET estimation by refining estimations of inter-thread interference.Our experiments demonstrate that the proposed approach can reasonably estimate inter-thread interference in shared caches and improve the tightness of WCET estimation by an average of 21% and 14%

compared with the estimations in literatures.

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