Optimization of MQ-Encoder and Implementation of High Speed VLSI Architecture

DI Zhi-xiong; SHI Jiang-yi; HAO Yue; Pang Jie; LIU Kai; LI Yun-song

doi:10.3969/j.issn.0372-2112.2012.11.003

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Optimization of MQ-Encoder and Implementation of High Speed VLSI Architecture

更新时间：2025-07-16

- Optimization of MQ-Encoder and Implementation of High Speed VLSI Architecture
- Acta Electronica Sinica Vol. 40, Issue 11, Pages: 2158-2164(2012)
- 作者机构：
  
  1. 西安电子科技大学宽禁带半导体材料与器件教育部重点实验室,陕西,西安,710071
  2. 西安电子科技大学ISN重点实验室,陕西,西安,710071
  3. 西安电子科技大学宽禁带半导体材料与器件教育部重点实验室陕西西安,710071
  4. 西安电子科技大学ISN重点实验室陕西西安,710071
- 作者简介：
- 基金信息：
  
  Fundamental Research Funds for the Central Universities (No.K50511010017)
- DOI：10.3969/j.issn.0372-2112.2012.11.003
  CLC： TP402
- Published：2012
- 稿件说明：
移动端阅览
DI Zhi-xiong, SHI Jiang-yi, HAO Yue, et al. Optimization of MQ-Encoder and Implementation of High Speed VLSI Architecture[J]. Acta Electronica Sinica, 2012, 40(11): 2158-2164.
DOI：

DI Zhi-xiong, SHI Jiang-yi, HAO Yue, et al. Optimization of MQ-Encoder and Implementation of High Speed VLSI Architecture[J]. Acta Electronica Sinica, 2012, 40(11): 2158-2164. DOI： 10.3969/j.issn.0372-2112.2012.11.003.

摘要

传统的JPEG2000MQ编码器串行编码效率低下

同时现有的多上下文并行编码的MQ编码器占用资源过大.本文对MQ编码算法中的运算流程

索引值和概率估计值的求解函数

条件交换和重归一化算法等四个方面进行了优化

减弱了上下文之间的依赖性

简化了条件交换和重归一化算法的复杂度.依据该算法

本文提出了一种高速的MQ编码器VLSI结构

实验结果表明

本文提出的MQ编码器VLSI结构能够工作在532.91MHz

吞吐率为532.91 Msymbols/sec

相比Dyer提出的Brute force with modified结构

工作频率提高1倍

吞吐量提高近27%

且面积仅为其四分之一.

Abstract

MQ-encoder

which is a key bottleneck in the JPEG2000 image compression system

presents challenges for realization of a high-speed and low cost VLSI architecture.In this paper

some optimization work has been done to the MQ-encoder arithmetic about the process flow

index and probably estimation function

condition change and renormalization.These optimization schemes are highly effective in simplifying the relation between contexts

reducing the complexity of the condition change and renormalization process

and cutting down the critical path delay of the pipeline.Based on this improved arithmetic

a VLSI architecture for an MQ-encoder with high speed is proposed.Synthesis result shows that the processing speed of the MQ-coder could reach as high as 532.91MHz with a throughput of 532.91 Msymbols/sec.Compared with Dyer’s architecture

the architecture with an improved throughput as high as 27% presented in this paper can get a speed two times greater than the former one while its area is only a quarter of the former one.

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