The fault probability of the elementary gate p for the reliability estimation of gate-level circuits had been given based on expert experience or as a constant generally.Considering the time change of properties of fault probability and the input-interconnects of different elementary gates

a fault probability model considering input loads and time factor is constructed.Theoretical analysis and experimental results show that the bimodal lognormal distribution based on weak link model is more suitable to describe the time distribution of the input-interconnect fault probability.The reliability values of ISCAS 85 benchmark circuits are calculated and compared by the iterative probability transfer matrix based on the proposed model

the reliability calculation method recommended by MIL-HDBK-217 standard and the reliability simulation method adopted by Monte Carlo.The industrial standard is also used to further test.It shows that the proposed model is reasonable.