Low Power Design of Asynchronous Datapath for LDPC Decoder

JIANG Xiao-bo; YE De-sheng; WU Wen-tao; XU Xiang-min

doi:10.3969/j.issn.0372-2112.2013.04.010

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Low Power Design of Asynchronous Datapath for LDPC Decoder

更新时间：2025-07-16

- Low Power Design of Asynchronous Datapath for LDPC Decoder
- Acta Electronica Sinica Vol. 41, Issue 4, Pages: 685-689(2013)
- 作者机构：
  
  华南理工大学电子与信息学院,广东,广州,510641
- 作者简介：
- 基金信息：
  
  National Natural Science Foundation of China (No.60976031);Science and Technology Department of Guangdong Province (No.2009B080701060, No.2010A080402015, No.2011A010801005);Fundamental Research of the Central Universities (No.2009ZM0310)
- DOI：10.3969/j.issn.0372-2112.2013.04.010
  CLC： TN914
- Published：2013
- 稿件说明：
移动端阅览
JIANG Xiao-bo, YE De-sheng, WU Wen-tao, et al. Low Power Design of Asynchronous Datapath for LDPC Decoder[J]. Acta Electronica Sinica, 2013, 41(4): 685-689.
DOI：

JIANG Xiao-bo, YE De-sheng, WU Wen-tao, et al. Low Power Design of Asynchronous Datapath for LDPC Decoder[J]. Acta Electronica Sinica, 2013, 41(4): 685-689. DOI： 10.3969/j.issn.0372-2112.2013.04.010.

摘要

本文设计了异步LDPC解码器运算通路

利用异步电路减少信号到达时间不一致引起的毛刺和时钟引起的功耗.利用输入数据的统计特性设计了运算通路中的主要运算单元

减少了冗余运算.本文还实现了同步运算通路和基于门控时钟的运算通路作为比较.三种设计采用相近的架构

在0.18μm CMOS工艺下实现相同的功能.仿真结果表明

提出的异步设计功耗最小

相比于同步设计和基于门控时钟设计

分别节省了42.0%和32.6%的功耗.虽然性能稍逊于同步设计

但优于门控时钟设计.其中

同步设计的延时是1.09ns

基于门控时钟的设计延时是1.61ns

而异步设计则是1.20ns.

Abstract

Asynchronous datapath of LDPC decoder is proposed in this paper.Glitches and redundant computations are decreased by asynchronous design.Clock tree is replaced by handshake control units.Taking advantages of input data statistical characteristic

key arithmetic elements in the datapath are proposed.Two types of datapaths including synchronous design and clock-gating design are also implemented as contrasts.Three designs exploit similar architecture and realize the same function by 0.18μm CMOS process.Simulation result shows that the proposed asynchronous design features the lowest power.Compared with the synchronous and clock-gating designs

it saves 42.0% and 32.6% power respectively.Its performance is a little bit worse than the synchronous design

but is better than the clock-gating design.The delay of the synchronous design is 1.09ns

the clock-gating design is 1.61ns

and the proposed design is 1.20ns.

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