Optimization of Two-Context MQ-Encoder and Implementation of VLSI Architecture

DI Zhi-xiong; SHI Jiang-yi; LIU Kai; LI Yun-song; MA Pei-jun; HAO Yue

doi:10.3969/j.issn.0372-2112.2013.05.014

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Optimization of Two-Context MQ-Encoder and Implementation of VLSI Architecture

更新时间：2025-07-16

- Optimization of Two-Context MQ-Encoder and Implementation of VLSI Architecture
- Acta Electronica Sinica Vol. 41, Issue 5, Pages: 918-925(2013)
- 作者机构：
  
  1. 西安电子科技大学宽带隙半导体技术国家重点学科实验室,陕西,西安,710071
  2. 西安电子科技大学ISN重点实验室,陕西,西安,710071
  3. 西安电子科技大学宽带隙半导体技术国家重点学科实验室陕西西安,710071
  4. 西安电子科技大学ISN重点实验室陕西西安,710071
- 作者简介：
- 基金信息：
- DOI：10.3969/j.issn.0372-2112.2013.05.014
  CLC： TP402
- Published：2013
- 稿件说明：
移动端阅览
DI Zhi-xiong, SHI Jiang-yi, LIU Kai, et al. Optimization of Two-Context MQ-Encoder and Implementation of VLSI Architecture[J]. Acta Electronica Sinica, 2013, 41(5): 918-925.
DOI：

DI Zhi-xiong, SHI Jiang-yi, LIU Kai, et al. Optimization of Two-Context MQ-Encoder and Implementation of VLSI Architecture[J]. Acta Electronica Sinica, 2013, 41(5): 918-925. DOI： 10.3969/j.issn.0372-2112.2013.05.014.

摘要

MQ(Multiple Quantization)编码器由于效率低下已经成为JPEG2000的性能瓶颈.本文对MQ编码算法中的上下文关系进行了提取

对索引表中的启动态和非暂态进行了分离

并提出一种用于预测索引值的方法.同时

对重归一化运算中出现的大概率事件和小概率事件进行分离

使其可并行对2个上下文完成编码.依据该算法

本文提出了一种多上下文并行处理的MQ编码器VLSI结构.实验结果表明

本文提出的MQ编码器能够工作在286.80MHz

吞吐量为573.60 Msymbols/sec

相比Dyer提出的Brute Force with Modified Byteout结构

本文的吞吐量提升约35%

且面积减小78%.

Abstract

MQ-encoder is a key bottleneck in the JPEG2000 image compression system.In this paper

the dependence between contexts in the MQ-encoder has been extracted;and an improved mechanism has been proposed to acquire indexes by separating the start-up states and remaining states.Besides

a prediction method has been proposed to resolve the stall problem when the current context is the same as the previous context.Also the probabilities of MPS and LPS coding events in the renormalization procedure have been analyzed;and either of the MPS and LPS coding events has been optimized.Based on this improved arithmetic

a VLSI architecture for Two-context MQ-encoder is proposed.Synthesis result shows that the processing speed of the MQ-encoder could reach as high as 286.80MHz with a throughput of 573.60Msymbols/sec.Compared with the Brute force with modified byteout architecture

the throughput obtained in this work has been improved by 35% and the area has been reduced by 78%.

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