LIU Zhong-jin, LI Yong, YANG Mao, et al. Design on Data Plane of Programmable Hardware-Based Virtual Router[J]. Acta Electronica Sinica, 2013, 41(7): 1268-1272.
DOI:
LIU Zhong-jin, LI Yong, YANG Mao, et al. Design on Data Plane of Programmable Hardware-Based Virtual Router[J]. Acta Electronica Sinica, 2013, 41(7): 1268-1272. DOI: 10.3969/j.issn.0372-2112.2013.07.004.
Design on Data Plane of Programmable Hardware-Based Virtual Router
Building virtualized network experiment platform is considered to be an effective method for network architecture innovation and validation.The structure and performance of the virtual router determines the capacity and flexibility of network experiment platform.In this article
the virtual router's data-plane architecture with parallel pipelines is presented.Combined with parallel packet classification and asynchronous pointer polling scheduling mechanisms
we implement isolated heterogeneous router instances on the same physical underlying.Prototype system is deployed on programmable hardware which is tested with software routers in real network environment.Experimental results show that compared with traditional single-pipeline architecture
our design get greater flexibility and parallelism and supports heterogeneous router instances operating independently;logic resources overhead and delay characteristics are not significantly increased while each router instance achieves wire-speed forwarding which is comparable with that hardware.