Design of an On-Chip LDO System with Large Loading Current

HU Jia-jun; CHEN Hou-peng; SONG Zhi-tang; WANG Qian; HONG Xiao; LI Xi; XU Wei-yi

doi:10.3969/j.issn.0372-2112.2013.07.029

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Design of an On-Chip LDO System with Large Loading Current

更新时间：2025-07-16

- Design of an On-Chip LDO System with Large Loading Current
- Acta Electronica Sinica Vol. 41, Issue 7, Pages: 1431-1435(2013)
- 作者机构：
  
  中国科学院上海微系统与信息技术研究所信息功能材料国家重点实验室,上海,200050
- 作者简介：
- 基金信息：
  
  Major Project of National Integrated Circuit (No.2009ZX02023-003);National Key Basic Research Development Plan (No.2007CB935400, No.2010CB934300, No.2011CB309602, No.2011CB932800);National Natural Science Foundation of China (No.60906004, No.60906003, No.61006087, No.61076121);Foundation of Shanghai Science and Technology Commission of Shanghai Municipality (No.09QH1402600, No.1052nm07000);Open Fund of State Laboratory of Electronic Thin Films and Integrated Devices (No.KFJJ201110)
- DOI：10.3969/j.issn.0372-2112.2013.07.029
  CLC： TN43
- Published：2013
- 稿件说明：
移动端阅览
HU Jia-jun, CHEN Hou-peng, SONG Zhi-tang, et al. Design of an On-Chip LDO System with Large Loading Current[J]. Acta Electronica Sinica, 2013, 41(7): 1431-1435.
DOI：

HU Jia-jun, CHEN Hou-peng, SONG Zhi-tang, et al. Design of an On-Chip LDO System with Large Loading Current[J]. Acta Electronica Sinica, 2013, 41(7): 1431-1435. DOI： 10.3969/j.issn.0372-2112.2013.07.029.

摘要

本文分析了传统大电流负载的LDO(Low-dropout Regulator)系统实现系统稳定性和瞬态响应提高的局限性

在此基础上

提出了一种片内集成的瞬态响应提高技术.此技术无需外挂电容和等效串联电阻(Equivalent Series Resistor

ESR)

即能使系统在全负载范围内保持稳定性和良好的纹波抑制能力.仿真结果表明

系统空载时

静态电流为64A

且最大能提供800mA的负载电流

1KHz时的电源抑制比达到-60dB

当负载电流以800mA/5s跳变时

最大下冲电压为400mV

上冲电压为536mV

恢复时间分别只需6.7s和12.8s

版图面积约为0.64mm

Abstract

This paper analyzes the stability and transient response enhancement limit of traditional LDO system and a transient response enhancement technique of on-chip LDO system is presented.Based on the analysis

a transient response enhancement technique fully integrated on-chip is put forward.The proposed scheme not only results in stability within a wide range of load variation

but also gets a good ripple rejection without off-chip capacitor and equivalent series resistor.It is demonstrated by simulation that the proposed circuit dissipates only 64A of quiescent current with empty load and it is capable of delivering load current up to 800mA

the power supply rejection rate at 1KHz is about -60dB.For a load step of 800mA/5s

the ci

rcuit has a maximum undershoot of 400mV and a maximum overshoot of 536mV.The recovery time is only 6.7s and 12.8s respectively and the layout area is about 0.64mm

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