The Optimization Circuit Design of AES S-Box Based on a Multiple-Term Common Subexpression Elimination Algorithm

ZENG Chun; WU Ning; ZHANG Xiao-qiang; ZHOU Fang; YE Yun-fei

doi:10.3969/j.issn.0372-2112.2014.06.032

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The Optimization Circuit Design of AES S-Box Based on a Multiple-Term Common Subexpression Elimination Algorithm

更新时间：2025-07-16

- The Optimization Circuit Design of AES S-Box Based on a Multiple-Term Common Subexpression Elimination Algorithm
- Acta Electronica Sinica Vol. 42, Issue 6, Pages: 1238-1243(2014)
- 作者机构：
  
  南京航空航天大学电子信息工程学院,江苏,南京,210016
- 作者简介：
- 基金信息：
- DOI：10.3969/j.issn.0372-2112.2014.06.032
  CLC： TN918.4
- Published：2014
- 稿件说明：
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ZENG Chun, WU Ning, ZHANG Xiao-qiang, et al. The Optimization Circuit Design of AES S-Box Based on a Multiple-Term Common Subexpression Elimination Algorithm[J]. Acta Electronica Sinica, 2014, 42(6): 1238-1243.
DOI：

ZENG Chun, WU Ning, ZHANG Xiao-qiang, et al. The Optimization Circuit Design of AES S-Box Based on a Multiple-Term Common Subexpression Elimination Algorithm[J]. Acta Electronica Sinica, 2014, 42(6): 1238-1243. DOI： 10.3969/j.issn.0372-2112.2014.06.032.

摘要

针对高级加密标准（AES）S-盒优化，提出了一种新的多因子公共项消除（CSE）优化算法.多因子CSE算法通过对组合逻辑表达式中所含因子最多的公共项优先消除，以简化逻辑表达式，从而有效地减少S-盒电路结构中的GF（2^4）域乘法逆电路和映射矩阵电路的面积和时延.结果表明，多因子CSE算法具有计算速度快，优化效率高的特点.优化后的S-盒组合逻辑电路采用0.18m CMOS工艺，设计出的S-盒面积-延时积比目前最小面积和最短延时的S-盒组合逻辑电路分别减少了10.32%和19.64%.

Abstract

Aiming at the optimization of advanced encryption standard (AES) S-box

a novel multiple-term common subexpression elimination (CSE) algorithm was proposed.In order to simplify the combinational logic expressions

the common subexpressions containing the most factors took priority to be eliminated in the proposed approach

thus effectively reduced the area and latency of the GF(2^4) multiplicative inverse circuit and the isomorphic mapping circuit in S-box.The results show that the multiple-term CSE algorithm achieves high computation and optimization efficiency.The optimized S-box is implemented in 0.18m CMOS technology.Compared with the smallest S-box and the shortest delay S-box in the existing work

the optimized S-box saves about 10.32% and 19.64% of the area-delay product separately.

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