A CMOS High-Speed Backplane Transmitter with 4 Reconfigurable Equalization Schemes

ZHU Xu-dong; CHEN Dian-yong; T.Kwasniewski

doi:10.3969/j.issn.0372-2112.2014.11.025

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A CMOS High-Speed Backplane Transmitter with 4 Reconfigurable Equalization Schemes

更新时间：2025-07-16

- A CMOS High-Speed Backplane Transmitter with 4 Reconfigurable Equalization Schemes
- Acta Electronica Sinica Vol. 42, Issue 11, Pages: 2291-2297(2014)
- 作者机构：
  
  1. 无锡工艺职业技术学院电子信息系,江苏,无锡,214231
  2. Carleton大学电子系,加拿大
- 作者简介：
- 基金信息：
- DOI：10.3969/j.issn.0372-2112.2014.11.025
  CLC： TN29
- Published：2014
- 稿件说明：
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ZHU Xu-dong, CHEN Dian-yong, T.Kwasniewski. A CMOS High-Speed Backplane Transmitter with 4 Reconfigurable Equalization Schemes[J]. Acta Electronica Sinica, 2014, 42(11): 2291-2297.
DOI：

ZHU Xu-dong, CHEN Dian-yong, T.Kwasniewski. A CMOS High-Speed Backplane Transmitter with 4 Reconfigurable Equalization Schemes[J]. Acta Electronica Sinica, 2014, 42(11): 2291-2297. DOI： 10.3969/j.issn.0372-2112.2014.11.025.

摘要

介绍了一种带有可重构的波特率有限冲激响应型均衡器的高速背板发射机电路.均衡器可以根据需要设置为基于脉冲幅度调制编码的数据中心优化型二电平均衡器和四电平均衡器、边沿优化型均衡器和双二进制均衡器

以及两倍速过采样均衡器.给出了均衡器设计与优化的步骤和公式

并利用90nm CMOS工艺制作了测试芯片.在40in背板上数据率为每秒10 Gbps的实验结果较好地符合了理论分析和设计目标.当电源电压为1.2V时

发射机功耗为70.3mW

能驱动50的背板

输出电平峰峰值为500mV.

Abstract

This paper presents a high-speed backplane transmitter with an equalizer that can be reconfigured to baud rate finite-impulse-response(FIR)data center 2-level pulse amplitude modulated(2-PAM)and 4-level pulse amplitude modulated(4-PAM)equalizer

edge equalizer

and duobinary equalizer.Equations to optimize the equalizer design are introduced.A test chip has been designed in 90nm CMOS.Experimental results on a 40in backplane at 10 gigabits-per-second(Gbps)match the theoretical analysis.The transmitter consumes 70.3mW of power from a 1.2V supply while driving 500mV peak to peak voltage.

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