Design of Highly Robust PUF Based on the Optimal Gate Voltage

WANG Peng-jun; ZHANG Xue-long; ZHANG Yue-jun

doi:10.3969/j.issn.0372-2112.2015.05.011

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Design of Highly Robust PUF Based on the Optimal Gate Voltage

更新时间：2025-07-16

- Design of Highly Robust PUF Based on the Optimal Gate Voltage
- Acta Electronica Sinica Vol. 43, Issue 5, Pages: 907-910(2015)
- 作者机构：
  
  宁波大学电路与系统研究所,浙江,宁波,315211
- 作者简介：
- 基金信息：
- DOI：10.3969/j.issn.0372-2112.2015.05.011
  CLC： TP331
- Published：2015
- 稿件说明：
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WANG Peng-jun, ZHANG Xue-long, ZHANG Yue-jun. Design of Highly Robust PUF Based on the Optimal Gate Voltage[J]. Acta Electronica Sinica, 2015, 43(5): 907-910.
DOI：

WANG Peng-jun, ZHANG Xue-long, ZHANG Yue-jun. Design of Highly Robust PUF Based on the Optimal Gate Voltage[J]. Acta Electronica Sinica, 2015, 43(5): 907-910. DOI： 10.3969/j.issn.0372-2112.2015.05.011.

摘要

物理不可克隆函数(Physical Unclonable Functions

PUF)电路作为一种新型的信息安全电路

依赖集成电路制造过程中硅器件的固有工艺偏差产生密钥.本文提出一种高鲁棒性PUF电路设计方案

首先分析MOSFET在零温度系数点(Zero Temperature Coefficient

ZTC)的工作特性

然后结合提高PUF电路鲁棒性的途径

确定PUF电路的结构及最优控制电压

最终达到密钥稳定可靠的目的.在TSMC 65nm CMOS工艺下对所设计的PUF电路进行版图设计

面积为14.89

m12.14

m.实验结果显示在最优控制电压下PUF电路的鲁棒性最低为96%.

Abstract

Physical Unclonable Functions (PUF)

as a kind of innovative secure circuits

extract key relying upon the intrinsic process variations in silicon devices.This paper proposes a scheme of highly robust PUF.First

we analyze the properties of the MOSFET working at the point of Zero Temperature Coefficient.And then we determine the structure and the optimal gate voltage of PUF by combining the approaches that improve the robustness of PUF circuits.All of which lead to the goal of making the keys stable and reliable at last.This design is implemented in TSMC 65nm CMOS technology and the layout area occupies 14.89

m12.14

m. The simulation results show that the reliability of PUF is not less than 96%

whi

ch is better than other PUF circuits.

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