WANG Xiang-qian, HONG Yi, WANG Hao, et al. Compiler Design and Optimization for BWDSP[J]. Acta Electronica Sinica, 2015, 43(8): 1656-1661.
DOI:
WANG Xiang-qian, HONG Yi, WANG Hao, et al. Compiler Design and Optimization for BWDSP[J]. Acta Electronica Sinica, 2015, 43(8): 1656-1661. DOI: 10.3969/j.issn.0372-2112.2015.08.028.
register allocation and instruction scheduling on clustering architecture.The key optimization technologies of BWDSP compiler on its hardware architecture include vectorization based on dependence analysis
application of effective instruction and recognization of zero overhead loop.Some general attention points for compiler development based on open source compiler infrastructure are presented after the development experience on BWDSP compiler is summarized.