An ultra-low power successive approximation register analog-to-digital converter for biomedical application is proposed.Many ultra-low power design methods are utilized for its main modules.The digital-to-analog converter (DAC) employs a vcm-based and split capacitor array structure to cut down the total capacitance

so as the power consumption.Voltage window technique is used to decrease the power consumption of the comparator without sacrificing its accuracy.Furthermore

stack forcing and multi-Vt design approaches are used to reduce the leakage current under low frequency.The proposed SAR ADC is designed and simulated in 55nm process.With 0.6V power supply and 10kS/s sampling rate

the ADC achieves a signal-to-noise-and-distortion-ratio (SNDR) of 73.3dB.The total power consumption is 432nW and the figure-of-merit (FOM) is 11.4fJ/Conv.