Efficiency Improvement of Doherty Power Amplifier Through Selection of the Power Transistor's Optimum Load Impedances

MA Chuan-hui; PAN Wen-sheng; SHAO Shi-hai; TANG You-xi

doi:10.3969/j.issn.0372-2112.2016.07.030

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Efficiency Improvement of Doherty Power Amplifier Through Selection of the Power Transistor's Optimum Load Impedances

更新时间：2025-07-16

- Efficiency Improvement of Doherty Power Amplifier Through Selection of the Power Transistor's Optimum Load Impedances
- Acta Electronica Sinica Vol. 44, Issue 7, Pages: 1728-1733(2016)
- 作者机构：
  
  电子科技大学通信抗干扰技术国家级重点实验室,四川,成都,611731
- 作者简介：
- 基金信息：
  
  National Natural Science Foundation of China (No.61271164, No.61471108, No.61201266)
- DOI：10.3969/j.issn.0372-2112.2016.07.030
  CLC： TN722
- Published：2016
- 稿件说明：
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MA Chuan-hui, PAN Wen-sheng, SHAO Shi-hai, et al. Efficiency Improvement of Doherty Power Amplifier Through Selection of the Power Transistor's Optimum Load Impedances[J]. Acta Electronica Sinica, 2016, 44(7): 1728-1733.
DOI：

MA Chuan-hui, PAN Wen-sheng, SHAO Shi-hai, et al. Efficiency Improvement of Doherty Power Amplifier Through Selection of the Power Transistor's Optimum Load Impedances[J]. Acta Electronica Sinica, 2016, 44(7): 1728-1733. DOI： 10.3969/j.issn.0372-2112.2016.07.030.

摘要

本文给出了一种提高Doherty功率放大器(DPA)效率的方法.为减轻非理想负载调制和膝点电压效应引起的DPA效率下降

首先分析得出了载波和峰值功放管负载阻抗应满足的要求

推导出了与载波放大器负载阻抗相关的等驻波比圆

并使用该圆得到了载波功放管的最优负载阻抗

以提高DPA的效率.根据所提方法设计并实现了一个工作在2.35GHz的非对称DPA.单音信号测试时

该放大器的饱和功率为49.3dBm

在峰值和8dB回退功率下其漏极效率分别高于68%和55%.五载波100MHz LTE-advanced信号激励下

输出功率40.5dBm时该放大器的平均效率为50.5%

其校正后的邻道泄露比(ACLR)低于-47.5dBc.实验结果表明

本文设计的非对称Doherty放大器具有较高的平均效率和良好的线性度性能

验证了所提方法的有效性.

Abstract

This paper presents an approach to improve the efficiency of the Doherty power amplifier.To mitigate the efficiency degradation resulting from the imperfect load modulation and the knee voltage effect

the requirements that the load impedances of the carrier and peaking transistors should meet were outlined.Subsequently

a constant voltage standing wave ratio (VSWR) circle that was related to the carrier amplifier's load impedances was derived and utilized to obtain the carrier transistor's optimum load impedances.For experimental validation

an asymmetrical DPA operating at 2.35GHz was designed and implemented.Tested with single tone continuous wave

the proposed DPA delivers a saturation power of about 49.3dBm and exhibits a drain efficiency of higher than 68% and 55% at peak and 8dB back-off power

respectively.When driven with 5 carriers 100MHz LTE-advanced signal

the DPA shows an average efficiency of 50.5% at 40.5dBm output power

along with an adjacent channel leakage ratio (ACLR) of lower than -47.5dBc after the digital pre-distortion (DPD) correction.The experimental results demonstrated that the proposed Doherty power amplifier has high average efficiency and good linearity performance

which verified the effectiveness of the proposed design approach.

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