A novel optional-iteration high speed and high precision CORDIC algorithm is proposed in this paper.First the rotation is conducted with a corresponding angle based on table-driven method.Then the algorithm bypasses unnecessary iterations using a new basic angle choosing technique.And the correction is achieved by shift and subtraction to reduce hardware consumption.Calculation and simulation indicate that the new algorithm can reduce the iteration number to less than 7 when the phase error is smaller than 10

-5

rad.In the application of DDFS

20 fractional binary bits design is implemented in Xilinx FPGA with range reduction method.This design can reduce amp

litude error to smaller than 210

-5

for sine and cosine

cut the output delay down to 43.5ns in circuit test

and no hardware consumption increase.